[PATCH] D18855: [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions

[Zlatko Buljan via llvm-commits]

zbuljan created this revision.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris.
Herald added subscribers: sdardis, dsanders.

The patch implements microMIPSr6 TLBP, TLBR, TLBWI and TLBWR instructions.

http://reviews.llvm.org/D18855

Files:
  lib/Target/Mips/MipsInstrInfo.td
  test/MC/Disassembler/Mips/micromips32r6/valid.txt
  test/MC/Disassembler/Mips/micromips64r6/valid.txt
  test/MC/Mips/micromips32r6/valid.s
  test/MC/Mips/micromips64r6/valid.s

Index: test/MC/Mips/micromips64r6/valid.s
===================================================================
--- test/MC/Mips/micromips64r6/valid.s
+++ test/MC/Mips/micromips64r6/valid.s
@@ -175,5 +175,9 @@
         dmfc0 $9, $1, 1          # CHECK: dmfc0 $9, $1, 1         # encoding: [0x59,0x21,0x08,0xfc]
         dmfc1 $9, $f4            # CHECK: dmfc1 $9, $f4           # encoding: [0x55,0x24,0x24,0x3b]
         dmfc2 $14, $18           # CHECK: dmfc2 $14, $18          # encoding: [0x01,0xd2,0x6d,0x3c]
+        tlbp                     # CHECK: tlbp                    # encoding: [0x00,0x00,0x03,0x7c]
+        tlbr                     # CHECK: tlbr                    # encoding: [0x00,0x00,0x13,0x7c]
+        tlbwi                    # CHECK: tlbwi                   # encoding: [0x00,0x00,0x23,0x7c]
+        tlbwr                    # CHECK: tlbwr                   # encoding: [0x00,0x00,0x33,0x7c]
 
 1:
Index: test/MC/Mips/micromips32r6/valid.s
===================================================================
--- test/MC/Mips/micromips32r6/valid.s
+++ test/MC/Mips/micromips32r6/valid.s
@@ -275,3 +275,7 @@
   mfhc0 $1, $2, 1          # CHECK: mfhc0 $1, $2, 1        # encoding: [0x00,0x22,0x08,0xf4]
   mfhc1 $zero, $f6         # CHECK: mfhc1 $zero, $f6       # encoding: [0x54,0x06,0x30,0x3b]
   mfhc2 $23, $16           # CHECK: mfhc2 $23, $16         # encoding: [0x02,0xf0,0x8d,0x3c]
+  tlbp                     # CHECK: tlbp                   # encoding: [0x00,0x00,0x03,0x7c]
+  tlbr                     # CHECK: tlbr                   # encoding: [0x00,0x00,0x13,0x7c]
+  tlbwi                    # CHECK: tlbwi                  # encoding: [0x00,0x00,0x23,0x7c]
+  tlbwr                    # CHECK: tlbwr                  # encoding: [0x00,0x00,0x33,0x7c]
Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -193,3 +193,7 @@
 0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1
 0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4
 0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18
+0x00 0x00 0x03 0x7c # CHECK: tlbp
+0x00 0x00 0x13 0x7c # CHECK: tlbr
+0x00 0x00 0x23 0x7c # CHECK: tlbwi
+0x00 0x00 0x33 0x7c # CHECK: tlbwr
Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -276,3 +276,7 @@
 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6
 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
+0x00 0x00 0x03 0x7c # CHECK: tlbp
+0x00 0x00 0x13 0x7c # CHECK: tlbr
+0x00 0x00 0x23 0x7c # CHECK: tlbwi
+0x00 0x00 0x33 0x7c # CHECK: tlbwr
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -2073,11 +2073,12 @@
 
 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
                                       FrmOther, asmstr>;
-def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
-def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
-def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
-def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
-
+let AdditionalPredicates = [NotInMicroMips] in {
+  def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
+  def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
+  def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
+  def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
+}
 class CacheOp<string instr_asm, Operand MemOpnd> :
     InstSE<(outs), (ins  MemOpnd:$addr, uimm5:$hint),
            !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,


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