[PATCH] D13649: [mips] Clang ll/sc illegal instruction on mips64r2 with -O0

[Simon Dardis via llvm-commits]

sdardis added a subscriber: sdardis.
sdardis added a comment.

This minimal test case:

  define {i16, i1} @foo(i16* %addr, i16 signext %r, i16 zeroext %new) {
    %res = cmpxchg i16* %addr, i16 %r, i16 %new seq_cst seq_cst
    ret {i16, i1} %res
  }

compiled for mips64r6 (big endian) with -target-abi=n64 -O0 shows the bug:
(irrelevant assembly removed)

  $BB0_1:                               # =>This Inner Loop Header: Depth=1
        lw      $1, 36($sp)             # 4-byte Folded Reload
        ll      $2, 0($1)

Which is sufficient to check that the change is correct.


================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:1506-1511
@@ +1505,8 @@
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::ANDi64 : Mips::ANDi),
+    MaskedCmpVal).addReg(CmpVal).addImm(MaskImm);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSLLV : Mips::SLLV), 
+    ShiftedCmpVal).addReg(MaskedCmpVal).addReg(ShiftAmt);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::ANDi64 : Mips::ANDi),
+    MaskedNewVal).addReg(NewVal).addImm(MaskImm);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSLLV : Mips::SLLV), 
+    ShiftedNewVal).addReg(MaskedNewVal).addReg(ShiftAmt);
----------------
Trailing whitespace on the lines with Mips::SLLV.


http://reviews.llvm.org/D13649