[PATCH] D18559: AMDGPU: Add a shader calling convention
Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 12:46:09 PDT 2016
This revision was automatically updated to reflect the committed changes.
Closed by commit rL265589: AMDGPU: Add a shader calling convention (authored by nha).
Changed prior to commit:
http://reviews.llvm.org/D18559?vs=51991&id=52838#toc
Repository:
rL LLVM
http://reviews.llvm.org/D18559
Files:
llvm/trunk/include/llvm/IR/CallingConv.h
llvm/trunk/lib/AsmParser/LLLexer.cpp
llvm/trunk/lib/AsmParser/LLParser.cpp
llvm/trunk/lib/AsmParser/LLToken.h
llvm/trunk/lib/IR/AsmWriter.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUCallingConv.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineFunction.h
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
llvm/trunk/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SITypeRewriter.cpp
llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/trunk/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll
llvm/trunk/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll
llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll
llvm/trunk/test/CodeGen/AMDGPU/bitcast.ll
llvm/trunk/test/CodeGen/AMDGPU/call_fs.ll
llvm/trunk/test/CodeGen/AMDGPU/cayman-loop-bug.ll
llvm/trunk/test/CodeGen/AMDGPU/commute-shifts.ll
llvm/trunk/test/CodeGen/AMDGPU/complex-folding.ll
llvm/trunk/test/CodeGen/AMDGPU/elf.ll
llvm/trunk/test/CodeGen/AMDGPU/fetch-limits.r600.ll
llvm/trunk/test/CodeGen/AMDGPU/fetch-limits.r700+.ll
llvm/trunk/test/CodeGen/AMDGPU/floor.ll
llvm/trunk/test/CodeGen/AMDGPU/fmad.ll
llvm/trunk/test/CodeGen/AMDGPU/fmax.ll
llvm/trunk/test/CodeGen/AMDGPU/fmin.ll
llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll
llvm/trunk/test/CodeGen/AMDGPU/input-mods.ll
llvm/trunk/test/CodeGen/AMDGPU/jump-address.ll
llvm/trunk/test/CodeGen/AMDGPU/large-alloca-graphics.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.gather4.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.getlod.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.image.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.image.sample.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.image.sample.o.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.packf16.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.tid.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.cos.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.pow.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.sin.ll
llvm/trunk/test/CodeGen/AMDGPU/load-input-fold.ll
llvm/trunk/test/CodeGen/AMDGPU/m0-spill.ll
llvm/trunk/test/CodeGen/AMDGPU/max-literals.ll
llvm/trunk/test/CodeGen/AMDGPU/mubuf.ll
llvm/trunk/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
llvm/trunk/test/CodeGen/AMDGPU/predicate-dp4.ll
llvm/trunk/test/CodeGen/AMDGPU/pv-packing.ll
llvm/trunk/test/CodeGen/AMDGPU/pv.ll
llvm/trunk/test/CodeGen/AMDGPU/r600-encoding.ll
llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll
llvm/trunk/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
llvm/trunk/test/CodeGen/AMDGPU/r600cfg.ll
llvm/trunk/test/CodeGen/AMDGPU/reciprocal.ll
llvm/trunk/test/CodeGen/AMDGPU/ret.ll
llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
llvm/trunk/test/CodeGen/AMDGPU/rv7x0_count3.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll
llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll
llvm/trunk/test/CodeGen/AMDGPU/shared-op-cycle.ll
llvm/trunk/test/CodeGen/AMDGPU/si-literal-folding.ll
llvm/trunk/test/CodeGen/AMDGPU/si-lod-bias.ll
llvm/trunk/test/CodeGen/AMDGPU/si-scheduler.ll
llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll
llvm/trunk/test/CodeGen/AMDGPU/si-spill-cf.ll
llvm/trunk/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
llvm/trunk/test/CodeGen/AMDGPU/smrd.ll
llvm/trunk/test/CodeGen/AMDGPU/split-smrd.ll
llvm/trunk/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
llvm/trunk/test/CodeGen/AMDGPU/swizzle-export.ll
llvm/trunk/test/CodeGen/AMDGPU/tex-clause-antidep.ll
llvm/trunk/test/CodeGen/AMDGPU/texture-input-merge.ll
llvm/trunk/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
llvm/trunk/test/CodeGen/AMDGPU/wait.ll
llvm/trunk/test/CodeGen/AMDGPU/wqm.ll
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