[llvm] r265487 - [RegisterBankInfo] Simplify the API for build a register bank.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Tue Apr  5 18:26:39 2016
New Revision: 265487

URL: http://llvm.org/viewvc/llvm-project?rev=265487&view=rev
Log:
[RegisterBankInfo] Simplify the API for build a register bank.
As part of the TRI argument of addRegBankCoverage we already have access to
the TargetRegisterClass through the ID of that register class.
Therefore, there is no point in needing a TargetRegisterClass instance,
the ID is enough to get to it.

Modified:
    llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
    llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h?rev=265487&r1=265486&r2=265487&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Tue Apr  5 18:26:39 2016
@@ -45,23 +45,23 @@ protected:
   /// \pre \p ID < NumRegBanks.
   void createRegisterBank(unsigned ID, const char *Name);
 
-  /// Add \p RC to the set of register class that the register bank
+  /// Add \p RCId to the set of register class that the register bank
   /// identified \p ID covers.
   /// This method transitively adds all the sub classes and the subreg-classes
-  /// of \p RC to the set of covered register classes.
+  /// of \p RCId to the set of covered register classes.
   /// It also adjusts the size of the register bank to reflect the maximal
   /// size of a value that can be hold into that register bank.
   ///
-  /// \note This method does *not* add the super classes of \p RC.
-  /// The rationale is if \p ID covers the registers of \p RC, that
+  /// \note This method does *not* add the super classes of \p RCId.
+  /// The rationale is if \p ID covers the registers of \p RCId, that
   /// does not necessarily mean that \p ID covers the set of registers
-  /// of RC's superclasses.
+  /// of RCId's superclasses.
   /// This method does *not* add the superreg classes as well for consistents.
   /// The expected use is to add the coverage top-down with respect to the
   /// register hierarchy.
   ///
   /// \todo TableGen should just generate the BitSet vector for us.
-  void addRegBankCoverage(unsigned ID, const TargetRegisterClass &RC,
+  void addRegBankCoverage(unsigned ID, unsigned RCId,
                           const TargetRegisterInfo &TRI);
 
   /// Get the register bank identified by \p ID.

Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=265487&r1=265486&r2=265487&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue Apr  5 18:26:39 2016
@@ -49,8 +49,7 @@ void RegisterBankInfo::createRegisterBan
   RegBank.Name = Name;
 }
 
-void RegisterBankInfo::addRegBankCoverage(unsigned ID,
-                                          const TargetRegisterClass &RC,
+void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
                                           const TargetRegisterInfo &TRI) {
   RegisterBank &RB = getRegBank(ID);
   unsigned NbOfRegClasses = TRI.getNumRegClasses();
@@ -60,7 +59,7 @@ void RegisterBankInfo::addRegBankCoverag
   // Check if RB is underconstruction.
   if (!RB.isValid())
     RB.ContainedRegClasses.resize(NbOfRegClasses);
-  else if (RB.contains(RC))
+  else if (RB.contains(*TRI.getRegClass(RCId)))
     // If RB already contains this register class, there is nothing
     // to do.
     return;
@@ -68,8 +67,8 @@ void RegisterBankInfo::addRegBankCoverag
   BitVector &Covered = RB.ContainedRegClasses;
   SmallVector<unsigned, 8> WorkList;
 
-  WorkList.push_back(RC.getID());
-  Covered.set(RC.getID());
+  WorkList.push_back(RCId);
+  Covered.set(RCId);
 
   unsigned &MaxSize = RB.Size;
   do {