[llvm] r265473 - [RegisterBank] Add printable capabilities for future debugging.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Tue Apr  5 16:40:43 2016
New Revision: 265473

URL: http://llvm.org/viewvc/llvm-project?rev=265473&view=rev
Log:
[RegisterBank] Add printable capabilities for future debugging.

Modified:
    llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
    llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp

Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h?rev=265473&r1=265472&r2=265473&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h Tue Apr  5 16:40:43 2016
@@ -19,6 +19,7 @@
 namespace llvm {
 // Forward declarations.
 class RegisterBankInfo;
+class raw_ostream;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 
@@ -73,7 +74,24 @@ public:
   bool operator!=(const RegisterBank &OtherRB) const {
     return !this->operator==(OtherRB);
   }
+
+  /// Dump the register mask on dbgs() stream.
+  /// The dump is verbose.
+  void dump(const TargetRegisterInfo *TRI = nullptr) const;
+
+  /// Print the register mask on OS.
+  /// If IsForDebug is false, then only the name of the register bank
+  /// is printed. Otherwise, all the fields are printing.
+  /// TRI is then used to print the name of the register classes that
+  /// this register bank covers.
+  void print(raw_ostream &OS, bool IsForDebug = false,
+             const TargetRegisterInfo *TRI = nullptr) const;
 };
+
+inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
+  RegBank.print(OS);
+  return OS;
+}
 } // End namespace llvm.
 
 #endif

Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp?rev=265473&r1=265472&r2=265473&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp Tue Apr  5 16:40:43 2016
@@ -48,3 +48,37 @@ bool RegisterBank::operator==(const Regi
          "ID does not uniquely identify a RegisterBank");
   return &OtherRB == this;
 }
+
+void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
+  print(dbgs(), /* IsForDebug */ true, TRI);
+}
+
+void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
+                         const TargetRegisterInfo *TRI) const {
+  OS << getName();
+  if (!IsForDebug)
+    return;
+  OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
+     << "isValid:" << isValid() << '\n'
+     << "Number of Covered register classes: " << ContainedRegClasses.count()
+     << '\n';
+  // Print all the subclasses if we can.
+  // This register classes may not be properly initialized yet.
+  if (!TRI || ContainedRegClasses.empty())
+    return;
+  assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
+         "TRI does not match the initialization process?");
+  bool IsFirst = true;
+  OS << "Covered register classes:\n";
+  for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
+    const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
+
+    if (!contains(RC))
+      continue;
+
+    if (!IsFirst)
+      OS << ", ";
+    OS << TRI->getRegClassName(&RC);
+    IsFirst = false;
+  }
+}