[llvm] r265455 - [TargetRegisterClass] Improve the comment for how to use getSubClassMask.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Tue Apr  5 15:21:53 2016
New Revision: 265455

URL: http://llvm.org/viewvc/llvm-project?rev=265455&view=rev
Log:
[TargetRegisterClass] Improve the comment for how to use getSubClassMask.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=265455&r1=265454&r2=265455&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Apr  5 15:21:53 2016
@@ -161,8 +161,21 @@ public:
   }
 
   /// Returns a bit vector of subclasses, including this one.
-  /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
-  /// use it.
+  /// The vector is indexed by class IDs.
+  ///
+  /// To use it, consider the returned array as a chunk of memory that
+  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
+  /// contains a bitset of the ID of the subclasses in big-endian style.
+
+  /// I.e., the representation of the memory from left to right at the
+  /// bit level looks like:
+  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
+  ///                     [ XXX NumRegClasses NumRegClasses - 1 ... ]
+  /// Where the number represents the class ID and XXX bits that
+  /// should be ignored.
+  ///
+  /// See the implementation of hasSubClassEq for an example of how it
+  /// can be used.
   const uint32_t *getSubClassMask() const {
     return SubClassMask;
   }