[PATCH] D18525: Add MachineFunctionProperty checks for AllVRegsAllocated for target passes

[Derek Schuff via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL265313: Add MachineFunctionProperty checks for AllVRegsAllocated for target passes (authored by dschuff).

Changed prior to commit:
  http://reviews.llvm.org/D18525?vs=51837&id=52577#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D18525

Files:
  llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
  llvm/trunk/lib/CodeGen/IfConversion.cpp
  llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp
  llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
  llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
  llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/trunk/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
  llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
  llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  llvm/trunk/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
  llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
  llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
  llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp
  llvm/trunk/lib/Target/Lanai/LanaiSetflagAluCombiner.cpp
  llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
  llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
  llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
  llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
  llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
  llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
  llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
  llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
  llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
  llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
  llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
  llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp
  llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
  llvm/trunk/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
  llvm/trunk/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir

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