[PATCH] D18751: [MachineCombiner] Support for floating-point FMA on ARM64

[Gerolf Hoflehner via llvm-commits]

Gerolf created this revision.
Gerolf added reviewers: qcolombet, t.p.northover, spatel.
Gerolf added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

Patch to evaluate fmul+fadd -> fmadd combines and similar code sequences in the
machine combiner. It adds support for float and double similar to the existing
integer implmentation. The key features of this patch are:
- DAGCombiner checks whether it should combine greedily or let the machine
  combiner do the evaluation. This is (initially) only supported for ARM64.
- It gives preference to throughput over latency: the heuristic used is to
  combine always in loops, but this can be chosen by the target. For in-order cores
  latency over throughput might be the better choice
- Support for fmadd, f(n)msub, fmla, fmls
- On by default at O3 fast-math
- Performance: (mostly) single digits gains on kernels and SPEC2006 fp

http://reviews.llvm.org/D18751

Files:
  include/llvm/CodeGen/MachineCombinerPattern.h
  include/llvm/CodeGen/SelectionDAGTargetInfo.h
  include/llvm/Target/TargetInstrInfo.h
  lib/CodeGen/MachineCombiner.cpp
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/TargetInstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.h
  lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
  lib/Target/AArch64/AArch64SelectionDAGInfo.h
  test/CodeGen/AArch64/arm64-fma-combines.ll
  test/CodeGen/AArch64/arm64-fml-combines.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D18751.52522.patch
Type: text/x-patch
Size: 49523 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160404/bef0dc62/attachment.bin>