[llvm] r265267 - [X86][SSE] Refreshed MOVMSK sign bit tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 3 11:59:42 PDT 2016
Author: rksimon
Date: Sun Apr 3 13:59:42 2016
New Revision: 265267
URL: http://llvm.org/viewvc/llvm-project?rev=265267&view=rev
Log:
[X86][SSE] Refreshed MOVMSK sign bit tests
Modified:
llvm/trunk/test/CodeGen/X86/movmsk.ll
Modified: llvm/trunk/test/CodeGen/X86/movmsk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movmsk.ll?rev=265267&r1=265266&r2=265267&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movmsk.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movmsk.ll Sun Apr 3 13:59:42 2016
@@ -1,12 +1,17 @@
-; RUN: llc -mcpu=core2 < %s | FileCheck %s
-; ModuleID = '<stdin>'
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-apple-macosx10.6.6"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.6.6 -mattr=+sse4.1 | FileCheck %s
%0 = type { double }
%union.anon = type { float }
define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp {
+; CHECK-LABEL: double_signbit:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: movsd %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movsd %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movmskpd %xmm0, %eax
+; CHECK-NEXT: andl $1, %eax
+; CHECK-NEXT: retq
entry:
%__x.addr.i = alloca double, align 8
%__u.i = alloca %0, align 8
@@ -16,15 +21,20 @@ entry:
%__f.i = getelementptr inbounds %0, %0* %__u.i, i64 0, i32 0
store double %d1, double* %__f.i, align 8
%tmp = bitcast double %d1 to i64
-; CHECK-NOT: shr
-; CHECK: movmskpd
-; CHECK-NEXT: and
%tmp1 = lshr i64 %tmp, 63
%shr.i = trunc i64 %tmp1 to i32
ret i32 %shr.i
}
define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp {
+; CHECK-LABEL: double_add_signbit:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: addsd %xmm1, %xmm0
+; CHECK-NEXT: movsd %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movsd %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movmskpd %xmm0, %eax
+; CHECK-NEXT: andl $1, %eax
+; CHECK-NEXT: retq
entry:
%__x.addr.i = alloca double, align 8
%__u.i = alloca %0, align 8
@@ -35,15 +45,19 @@ entry:
%__f.i = getelementptr inbounds %0, %0* %__u.i, i64 0, i32 0
store double %add, double* %__f.i, align 8
%tmp = bitcast double %add to i64
-; CHECK-NOT: shr
-; CHECK: movmskpd
-; CHECK-NEXT: and
%tmp1 = lshr i64 %tmp, 63
%shr.i = trunc i64 %tmp1 to i32
ret i32 %shr.i
}
define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp {
+; CHECK-LABEL: float_signbit:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: movss %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movss %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movmskps %xmm0, %eax
+; CHECK-NEXT: andl $1, %eax
+; CHECK-NEXT: retq
entry:
%__x.addr.i = alloca float, align 4
%__u.i = alloca %union.anon, align 4
@@ -53,14 +67,19 @@ entry:
%__f.i = getelementptr inbounds %union.anon, %union.anon* %__u.i, i64 0, i32 0
store float %f1, float* %__f.i, align 4
%2 = bitcast float %f1 to i32
-; CHECK-NOT: shr
-; CHECK: movmskps
-; CHECK-NEXT: and
%shr.i = lshr i32 %2, 31
ret i32 %shr.i
}
define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp {
+; CHECK-LABEL: float_add_signbit:
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: addss %xmm1, %xmm0
+; CHECK-NEXT: movss %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movss %xmm0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: movmskps %xmm0, %eax
+; CHECK-NEXT: andl $1, %eax
+; CHECK-NEXT: retq
entry:
%__x.addr.i = alloca float, align 4
%__u.i = alloca %union.anon, align 4
@@ -71,21 +90,20 @@ entry:
%__f.i = getelementptr inbounds %union.anon, %union.anon* %__u.i, i64 0, i32 0
store float %add, float* %__f.i, align 4
%2 = bitcast float %add to i32
-; CHECK-NOT: shr
-; CHECK: movmskps
-; CHECK-NEXT: and
%shr.i = lshr i32 %2, 31
ret i32 %shr.i
}
; PR11570
-define void @float_call_signbit(double %n) {
-entry:
; FIXME: This should also use movmskps; we don't form the FGETSIGN node
; in this case, though.
+define void @float_call_signbit(double %n) {
; CHECK-LABEL: float_call_signbit:
-; CHECK: movd %xmm0, %rdi
-; FIXME
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: movd %xmm0, %rdi
+; CHECK-NEXT: shrq $63, %rdi
+; CHECK-NEXT: jmp _float_call_signbit_callee ## TAILCALL
+entry:
%t0 = bitcast double %n to i64
%tobool.i.i.i.i = icmp slt i64 %t0, 0
tail call void @float_call_signbit_callee(i1 zeroext %tobool.i.i.i.i)
@@ -98,10 +116,12 @@ declare void @float_call_signbit_callee(
; movmskp{s|d} only set low 4/2 bits, high bits are known zero
define i32 @t1(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
-entry:
; CHECK-LABEL: t1:
-; CHECK: movmskps
-; CHECK-NOT: movslq
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: movmskps %xmm0, %eax
+; CHECK-NEXT: movl (%rdi,%rax,4), %eax
+; CHECK-NEXT: retq
+entry:
%0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
%idxprom = sext i32 %0 to i64
%arrayidx = getelementptr inbounds i32, i32* %indexTable, i64 %idxprom
@@ -110,10 +130,12 @@ entry:
}
define i32 @t2(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
-entry:
; CHECK-LABEL: t2:
-; CHECK: movmskpd
-; CHECK-NOT: movslq
+; CHECK: ## BB#0: ## %entry
+; CHECK-NEXT: movmskpd %xmm0, %eax
+; CHECK-NEXT: movl (%rdi,%rax,4), %eax
+; CHECK-NEXT: retq
+entry:
%0 = bitcast <4 x float> %x to <2 x double>
%1 = tail call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %0) nounwind
%idxprom = sext i32 %1 to i64
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