[PATCH] D18602: AMDGPU/SI: Enable the post-ra scheduler

[Nicolai Hähnle via llvm-commits]

nhaehnle added a subscriber: nhaehnle.

================
Comment at: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:375
@@ +374,3 @@
+  if (getOptLevel() == CodeGenOpt::None)
+    addPass(&PostRAHazardRecognizerID);
+
----------------
Where is this added?

================
Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:40-46
@@ +39,9 @@
+
+  // Update the current wait states for registers.
+  for (auto &KV : RegDefs)
+    KV.second += NumWaitStates;
+
+  // Add registers defined by this instruction.
+  for (const MachineOperand &MO : MI->defs())
+    RegDefs[MO.getReg()] = 0;
+
----------------
It seems RegDefs isn't actually used anywhere?

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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:116-117
@@ +115,4 @@
+      continue;
+    if (MI->definesRegister(Reg))
+      return WaitStates;
+  }
----------------
Are you sure this does the right thing? According to the comment, definesRegister only returns true if the instruction defines a super-register of Reg, but there is probably also a hazard if it defines a sub-register.

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Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:1198
@@ +1197,3 @@
+    if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) {
+      // FIXME: Handle ds_ead2 / ds_write2.
+      return false;
----------------
Typo: ds_read2


http://reviews.llvm.org/D18602