[llvm] r265163 - [X86][SSE] Regenerated the vec_set tests.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 1 10:40:26 PDT 2016
Author: rksimon
Date: Fri Apr 1 12:40:25 2016
New Revision: 265163
URL: http://llvm.org/viewvc/llvm-project?rev=265163&view=rev
Log:
[X86][SSE] Regenerated the vec_set tests.
Replaced lots of dodgy greps with actual codegen
Modified:
llvm/trunk/test/CodeGen/X86/vec_set-2.ll
llvm/trunk/test/CodeGen/X86/vec_set-3.ll
llvm/trunk/test/CodeGen/X86/vec_set-4.ll
llvm/trunk/test/CodeGen/X86/vec_set-6.ll
llvm/trunk/test/CodeGen/X86/vec_set-7.ll
llvm/trunk/test/CodeGen/X86/vec_set-8.ll
llvm/trunk/test/CodeGen/X86/vec_set-A.ll
llvm/trunk/test/CodeGen/X86/vec_set-B.ll
llvm/trunk/test/CodeGen/X86/vec_set-C.ll
llvm/trunk/test/CodeGen/X86/vec_set-D.ll
llvm/trunk/test/CodeGen/X86/vec_set-F.ll
llvm/trunk/test/CodeGen/X86/vec_set-H.ll
llvm/trunk/test/CodeGen/X86/vec_set.ll
Modified: llvm/trunk/test/CodeGen/X86/vec_set-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-2.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-2.ll Fri Apr 1 12:40:25 2016
@@ -1,19 +1,27 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss | count 1
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,-sse4.1 | FileCheck %s
define <4 x float> @test1(float %a) nounwind {
- %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0 ; <<4 x float>> [#uses=1]
- %tmp5 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
- %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
- %tmp7 = insertelement <4 x float> %tmp6, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
- ret <4 x float> %tmp7
+; CHECK-LABEL: test1:
+; CHECK: # BB#0:
+; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: retl
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0
+ %tmp5 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1
+ %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 2
+ %tmp7 = insertelement <4 x float> %tmp6, float 0.000000e+00, i32 3
+ ret <4 x float> %tmp7
}
define <2 x i64> @test(i32 %a) nounwind {
- %tmp = insertelement <4 x i32> zeroinitializer, i32 %a, i32 0 ; <<8 x i16>> [#uses=1]
- %tmp6 = insertelement <4 x i32> %tmp, i32 0, i32 1 ; <<8 x i32>> [#uses=1]
- %tmp8 = insertelement <4 x i32> %tmp6, i32 0, i32 2 ; <<8 x i32>> [#uses=1]
- %tmp10 = insertelement <4 x i32> %tmp8, i32 0, i32 3 ; <<8 x i32>> [#uses=1]
- %tmp19 = bitcast <4 x i32> %tmp10 to <2 x i64> ; <<2 x i64>> [#uses=1]
- ret <2 x i64> %tmp19
+; CHECK-LABEL: test:
+; CHECK: # BB#0:
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: retl
+ %tmp = insertelement <4 x i32> zeroinitializer, i32 %a, i32 0
+ %tmp6 = insertelement <4 x i32> %tmp, i32 0, i32 1
+ %tmp8 = insertelement <4 x i32> %tmp6, i32 0, i32 2
+ %tmp10 = insertelement <4 x i32> %tmp8, i32 0, i32 3
+ %tmp19 = bitcast <4 x i32> %tmp10 to <2 x i64>
+ ret <2 x i64> %tmp19
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-3.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-3.ll Fri Apr 1 12:40:25 2016
@@ -1,11 +1,11 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+sse4.1 | FileCheck %s
define <4 x float> @test(float %a) {
; CHECK-LABEL: test:
-; CHECK: insertps $29, {{.*}}, %xmm0
+; CHECK: # BB#0:
+; CHECK-NEXT: insertps {{.*#+}} xmm0 = zero,mem[0],zero,zero
; CHECK-NEXT: retl
-
-entry:
%tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1
%tmp5 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 2
%tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3
@@ -14,11 +14,10 @@ entry:
define <2 x i64> @test2(i32 %a) {
; CHECK-LABEL: test2:
-; CHECK: movd {{.*}}, %xmm0
+; CHECK: # BB#0:
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,0,1]
; CHECK-NEXT: retl
-
-entry:
%tmp7 = insertelement <4 x i32> zeroinitializer, i32 %a, i32 2
%tmp9 = insertelement <4 x i32> %tmp7, i32 0, i32 3
%tmp10 = bitcast <4 x i32> %tmp9 to <2 x i64>
@@ -27,9 +26,9 @@ entry:
define <4 x float> @test3(<4 x float> %A) {
; CHECK-LABEL: test3:
-; CHECK: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
+; CHECK: # BB#0:
+; CHECK-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
; CHECK-NEXT: retl
-
%tmp0 = extractelement <4 x float> %A, i32 0
%tmp1 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef >, float %tmp0, i32 1
%tmp2 = insertelement <4 x float> %tmp1, float 0.000000e+00, i32 2
Modified: llvm/trunk/test/CodeGen/X86/vec_set-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-4.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-4.ll Fri Apr 1 12:40:25 2016
@@ -1,24 +1,34 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pinsrw | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
define <2 x i64> @test(i16 %a) nounwind {
-entry:
- %tmp10 = insertelement <8 x i16> zeroinitializer, i16 %a, i32 3 ; <<8 x i16>> [#uses=1]
- %tmp12 = insertelement <8 x i16> %tmp10, i16 0, i32 4 ; <<8 x i16>> [#uses=1]
- %tmp14 = insertelement <8 x i16> %tmp12, i16 0, i32 5 ; <<8 x i16>> [#uses=1]
- %tmp16 = insertelement <8 x i16> %tmp14, i16 0, i32 6 ; <<8 x i16>> [#uses=1]
- %tmp18 = insertelement <8 x i16> %tmp16, i16 0, i32 7 ; <<8 x i16>> [#uses=1]
- %tmp19 = bitcast <8 x i16> %tmp18 to <2 x i64> ; <<2 x i64>> [#uses=1]
- ret <2 x i64> %tmp19
+; CHECK-LABEL: test:
+; CHECK: # BB#0:
+; CHECK-NEXT: pxor %xmm0, %xmm0
+; CHECK-NEXT: pinsrw $3, {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: retl
+ %tmp10 = insertelement <8 x i16> zeroinitializer, i16 %a, i32 3
+ %tmp12 = insertelement <8 x i16> %tmp10, i16 0, i32 4
+ %tmp14 = insertelement <8 x i16> %tmp12, i16 0, i32 5
+ %tmp16 = insertelement <8 x i16> %tmp14, i16 0, i32 6
+ %tmp18 = insertelement <8 x i16> %tmp16, i16 0, i32 7
+ %tmp19 = bitcast <8 x i16> %tmp18 to <2 x i64>
+ ret <2 x i64> %tmp19
}
define <2 x i64> @test2(i8 %a) nounwind {
-entry:
- %tmp24 = insertelement <16 x i8> zeroinitializer, i8 %a, i32 10 ; <<16 x i8>> [#uses=1]
- %tmp26 = insertelement <16 x i8> %tmp24, i8 0, i32 11 ; <<16 x i8>> [#uses=1]
- %tmp28 = insertelement <16 x i8> %tmp26, i8 0, i32 12 ; <<16 x i8>> [#uses=1]
- %tmp30 = insertelement <16 x i8> %tmp28, i8 0, i32 13 ; <<16 x i8>> [#uses=1]
- %tmp32 = insertelement <16 x i8> %tmp30, i8 0, i32 14 ; <<16 x i8>> [#uses=1]
- %tmp34 = insertelement <16 x i8> %tmp32, i8 0, i32 15 ; <<16 x i8>> [#uses=1]
- %tmp35 = bitcast <16 x i8> %tmp34 to <2 x i64> ; <<2 x i64>> [#uses=1]
- ret <2 x i64> %tmp35
+; CHECK-LABEL: test2:
+; CHECK: # BB#0:
+; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: pxor %xmm0, %xmm0
+; CHECK-NEXT: pinsrw $5, %eax, %xmm0
+; CHECK-NEXT: retl
+ %tmp24 = insertelement <16 x i8> zeroinitializer, i8 %a, i32 10
+ %tmp26 = insertelement <16 x i8> %tmp24, i8 0, i32 11
+ %tmp28 = insertelement <16 x i8> %tmp26, i8 0, i32 12
+ %tmp30 = insertelement <16 x i8> %tmp28, i8 0, i32 13
+ %tmp32 = insertelement <16 x i8> %tmp30, i8 0, i32 14
+ %tmp34 = insertelement <16 x i8> %tmp32, i8 0, i32 15
+ %tmp35 = bitcast <16 x i8> %tmp34 to <2 x i64>
+ ret <2 x i64> %tmp35
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-6.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-6.ll Fri Apr 1 12:40:25 2016
@@ -1,12 +1,16 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
-; RUN: grep movss %t | count 1
-; RUN: grep movsd %t | count 1
-; RUN: grep shufps %t | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+sse4.1 | FileCheck %s
define <4 x float> @test(float %a, float %b, float %c) nounwind {
- %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1 ; <<4 x float>> [#uses=1]
- %tmp8 = insertelement <4 x float> %tmp, float %b, i32 2 ; <<4 x float>> [#uses=1]
- %tmp10 = insertelement <4 x float> %tmp8, float %c, i32 3 ; <<4 x float>> [#uses=1]
- ret <4 x float> %tmp10
+; CHECK-LABEL: test:
+; CHECK: # BB#0:
+; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1]
+; CHECK-NEXT: retl
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1
+ %tmp8 = insertelement <4 x float> %tmp, float %b, i32 2
+ %tmp10 = insertelement <4 x float> %tmp8, float %c, i32 3
+ ret <4 x float> %tmp10
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-7.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-7.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-7.ll Fri Apr 1 12:40:25 2016
@@ -1,11 +1,17 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
define <2 x i64> @test(<2 x i64>* %p) nounwind {
- %tmp = bitcast <2 x i64>* %p to double*
- %tmp.upgrd.1 = load double, double* %tmp
- %tmp.upgrd.2 = insertelement <2 x double> undef, double %tmp.upgrd.1, i32 0
- %tmp5 = insertelement <2 x double> %tmp.upgrd.2, double 0.0, i32 1
- %tmp.upgrd.3 = bitcast <2 x double> %tmp5 to <2 x i64>
- ret <2 x i64> %tmp.upgrd.3
+; CHECK-LABEL: test:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: retl
+ %tmp = bitcast <2 x i64>* %p to double*
+ %tmp.upgrd.1 = load double, double* %tmp
+ %tmp.upgrd.2 = insertelement <2 x double> undef, double %tmp.upgrd.1, i32 0
+ %tmp5 = insertelement <2 x double> %tmp.upgrd.2, double 0.0, i32 1
+ %tmp.upgrd.3 = bitcast <2 x double> %tmp5 to <2 x i64>
+ ret <2 x i64> %tmp.upgrd.3
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-8.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-8.ll Fri Apr 1 12:40:25 2016
@@ -1,13 +1,12 @@
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=-avx | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-win32 -mattr=-avx | FileCheck %s
-; CHECK-NOT: movsd
-; CHECK: movd {{%rdi|%rcx}}, %xmm0
-; CHECK-NOT: movsd
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s
define <2 x i64> @test(i64 %i) nounwind {
-entry:
- %tmp10 = insertelement <2 x i64> undef, i64 %i, i32 0
- %tmp11 = insertelement <2 x i64> %tmp10, i64 0, i32 1
- ret <2 x i64> %tmp11
+; CHECK-LABEL: test:
+; CHECK: # BB#0:
+; CHECK-NEXT: movd %rdi, %xmm0
+; CHECK-NEXT: retq
+ %tmp10 = insertelement <2 x i64> undef, i64 %i, i32 0
+ %tmp11 = insertelement <2 x i64> %tmp10, i64 0, i32 1
+ ret <2 x i64> %tmp11
}
-
Modified: llvm/trunk/test/CodeGen/X86/vec_set-A.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-A.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-A.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-A.ll Fri Apr 1 12:40:25 2016
@@ -1,7 +1,12 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
-; CHECK: movl $1, %{{.*}}
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
+
define <2 x i64> @test1() nounwind {
-entry:
- ret <2 x i64> < i64 1, i64 0 >
+; CHECK-LABEL: test1:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: retl
+ ret <2 x i64> < i64 1, i64 0 >
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-B.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-B.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-B.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-B.ll Fri Apr 1 12:40:25 2016
@@ -1,7 +1,5 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep esp | count 2
-
-; CHECK-NOT: movaps
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
; These should both generate something like this:
;_test3:
@@ -11,16 +9,26 @@
; ret
define <2 x i64> @test3(i64 %arg) nounwind {
-entry:
- %A = and i64 %arg, 1234567
- %B = insertelement <2 x i64> zeroinitializer, i64 %A, i32 0
- ret <2 x i64> %B
+; CHECK-LABEL: test3:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl $1234567, %eax # imm = 0x12D687
+; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: retl
+ %A = and i64 %arg, 1234567
+ %B = insertelement <2 x i64> zeroinitializer, i64 %A, i32 0
+ ret <2 x i64> %B
}
define <2 x i64> @test2(i64 %arg) nounwind {
-entry:
- %A = and i64 %arg, 1234567
- %B = insertelement <2 x i64> undef, i64 %A, i32 0
- ret <2 x i64> %B
+; CHECK-LABEL: test2:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl $1234567, %eax # imm = 0x12D687
+; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: retl
+ %A = and i64 %arg, 1234567
+ %B = insertelement <2 x i64> undef, i64 %A, i32 0
+ ret <2 x i64> %B
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-C.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-C.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-C.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-C.ll Fri Apr 1 12:40:25 2016
@@ -1,8 +1,17 @@
-; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+sse2,-avx | grep movq
-; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+sse2,-avx | grep mov | count 1
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-pc-linux -mattr=+sse2,-avx | grep movd
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-linux-gnu -mattr=+sse2,-avx | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2,-avx | FileCheck %s --check-prefix=X64
define <2 x i64> @t1(i64 %x) nounwind {
- %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
- ret <2 x i64> %tmp8
+; X32-LABEL: t1:
+; X32: # BB#0:
+; X32-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT: retl
+;
+; X64-LABEL: t1:
+; X64: # BB#0:
+; X64-NEXT: movd %rdi, %xmm0
+; X64-NEXT: retq
+ %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
+ ret <2 x i64> %tmp8
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-D.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-D.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-D.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-D.ll Fri Apr 1 12:40:25 2016
@@ -1,9 +1,12 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
-
-; CHECK: movq
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
define <4 x i32> @t(i32 %x, i32 %y) nounwind {
- %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
- %tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
- ret <4 x i32> %tmp2
+; CHECK-LABEL: t:
+; CHECK: # BB#0:
+; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: retl
+ %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
+ %tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
+ ret <4 x i32> %tmp2
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-F.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-F.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-F.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-F.ll Fri Apr 1 12:40:25 2016
@@ -1,19 +1,27 @@
-; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movq
-; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movsd
-; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep mov | count 3
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | FileCheck %s
define <2 x i64> @t1(<2 x i64>* %ptr) nounwind {
- %tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>*
- %tmp615 = load <2 x i32>, <2 x i32>* %tmp45
- %tmp7 = bitcast <2 x i32> %tmp615 to i64
- %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
- ret <2 x i64> %tmp8
+; CHECK-LABEL: t1:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: retl
+ %tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>*
+ %tmp615 = load <2 x i32>, <2 x i32>* %tmp45
+ %tmp7 = bitcast <2 x i32> %tmp615 to i64
+ %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
+ ret <2 x i64> %tmp8
}
define <2 x i64> @t2(i64 %x) nounwind {
- %tmp717 = bitcast i64 %x to double
- %tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0
- %tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1
- %tmp11 = bitcast <2 x double> %tmp9 to <2 x i64>
- ret <2 x i64> %tmp11
+; CHECK-LABEL: t2:
+; CHECK: # BB#0:
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: retl
+ %tmp717 = bitcast i64 %x to double
+ %tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0
+ %tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1
+ %tmp11 = bitcast <2 x double> %tmp9 to <2 x i64>
+ ret <2 x i64> %tmp11
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set-H.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-H.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-H.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-H.ll Fri Apr 1 12:40:25 2016
@@ -1,15 +1,21 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movz
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
define <2 x i64> @doload64(i16 signext %x) nounwind {
-entry:
- %tmp36 = insertelement <8 x i16> undef, i16 %x, i32 0 ; <<8 x i16>> [#uses=1]
- %tmp37 = insertelement <8 x i16> %tmp36, i16 %x, i32 1 ; <<8 x i16>> [#uses=1]
- %tmp38 = insertelement <8 x i16> %tmp37, i16 %x, i32 2 ; <<8 x i16>> [#uses=1]
- %tmp39 = insertelement <8 x i16> %tmp38, i16 %x, i32 3 ; <<8 x i16>> [#uses=1]
- %tmp40 = insertelement <8 x i16> %tmp39, i16 %x, i32 4 ; <<8 x i16>> [#uses=1]
- %tmp41 = insertelement <8 x i16> %tmp40, i16 %x, i32 5 ; <<8 x i16>> [#uses=1]
- %tmp42 = insertelement <8 x i16> %tmp41, i16 %x, i32 6 ; <<8 x i16>> [#uses=1]
- %tmp43 = insertelement <8 x i16> %tmp42, i16 %x, i32 7 ; <<8 x i16>> [#uses=1]
- %tmp46 = bitcast <8 x i16> %tmp43 to <2 x i64> ; <<2 x i64>> [#uses=1]
- ret <2 x i64> %tmp46
+; CHECK-LABEL: doload64:
+; CHECK: # BB#0:
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
+; CHECK-NEXT: retl
+ %tmp36 = insertelement <8 x i16> undef, i16 %x, i32 0
+ %tmp37 = insertelement <8 x i16> %tmp36, i16 %x, i32 1
+ %tmp38 = insertelement <8 x i16> %tmp37, i16 %x, i32 2
+ %tmp39 = insertelement <8 x i16> %tmp38, i16 %x, i32 3
+ %tmp40 = insertelement <8 x i16> %tmp39, i16 %x, i32 4
+ %tmp41 = insertelement <8 x i16> %tmp40, i16 %x, i32 5
+ %tmp42 = insertelement <8 x i16> %tmp41, i16 %x, i32 6
+ %tmp43 = insertelement <8 x i16> %tmp42, i16 %x, i32 7
+ %tmp46 = bitcast <8 x i16> %tmp43 to <2 x i64>
+ ret <2 x i64> %tmp46
}
Modified: llvm/trunk/test/CodeGen/X86/vec_set.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set.ll?rev=265163&r1=265162&r2=265163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set.ll Fri Apr 1 12:40:25 2016
@@ -1,15 +1,36 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | grep punpckl | count 7
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,-sse4.1 | FileCheck %s
define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
- %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]
- %tmp2 = insertelement <8 x i16> %tmp, i16 %a1, i32 1 ; <<8 x i16>> [#uses=1]
- %tmp4 = insertelement <8 x i16> %tmp2, i16 %a2, i32 2 ; <<8 x i16>> [#uses=1]
- %tmp6 = insertelement <8 x i16> %tmp4, i16 %a3, i32 3 ; <<8 x i16>> [#uses=1]
- %tmp8 = insertelement <8 x i16> %tmp6, i16 %a4, i32 4 ; <<8 x i16>> [#uses=1]
- %tmp10 = insertelement <8 x i16> %tmp8, i16 %a5, i32 5 ; <<8 x i16>> [#uses=1]
- %tmp12 = insertelement <8 x i16> %tmp10, i16 %a6, i32 6 ; <<8 x i16>> [#uses=1]
- %tmp14 = insertelement <8 x i16> %tmp12, i16 %a7, i32 7 ; <<8 x i16>> [#uses=1]
- store <8 x i16> %tmp14, <8 x i16>* %b
- ret void
+; CHECK-LABEL: test:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; CHECK-NEXT: movdqa %xmm3, (%eax)
+; CHECK-NEXT: retl
+ %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0
+ %tmp2 = insertelement <8 x i16> %tmp, i16 %a1, i32 1
+ %tmp4 = insertelement <8 x i16> %tmp2, i16 %a2, i32 2
+ %tmp6 = insertelement <8 x i16> %tmp4, i16 %a3, i32 3
+ %tmp8 = insertelement <8 x i16> %tmp6, i16 %a4, i32 4
+ %tmp10 = insertelement <8 x i16> %tmp8, i16 %a5, i32 5
+ %tmp12 = insertelement <8 x i16> %tmp10, i16 %a6, i32 6
+ %tmp14 = insertelement <8 x i16> %tmp12, i16 %a7, i32 7
+ store <8 x i16> %tmp14, <8 x i16>* %b
+ ret void
}
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