[llvm] r265134 - [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA

[Sagar Thakur via llvm-commits]

Author: slthakur
Date: Fri Apr  1 06:55:33 2016
New Revision: 265134

URL: http://llvm.org/viewvc/llvm-project?rev=265134&view=rev
Log:
[MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA

Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6.

Author: nitesh.jain
Reviewers: vkalintiris, dsanders
Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: D18387

Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/MC/Mips/mips32r6/valid.s
    llvm/trunk/test/MC/Mips/mips64r6/valid.s

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=265134&r1=265133&r2=265134&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Apr  1 06:55:33 2016
@@ -1809,7 +1809,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<
 /// Jump and Branch Instructions
 def J       : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
               AdditionalRequires<[RelocStatic]>, IsBranch;
-def JR      : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
+def JR      : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; 
 def BEQ     : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
 def BEQL    : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
               BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;

Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=265134&r1=265133&r2=265134&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Fri Apr  1 06:55:33 2016
@@ -161,6 +161,8 @@ a:
         j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jal       21100                # CHECK: jal 21100     # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
+        jr      $ra              # CHECK: jr $ra                 # encoding: [0x03,0xe0,0x00,0x09]
+        jr      $25              # CHECK: jr $25                 # encoding: [0x03,0x20,0x00,0x09]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]

Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=265134&r1=265133&r2=265134&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Fri Apr  1 06:55:33 2016
@@ -140,6 +140,8 @@ a:
         j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jal     21100            # CHECK: jal 21100              # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
+        jr      $ra              # CHECK: jr $ra                 # encoding: [0x03,0xe0,0x00,0x09]
+        jr      $25              # CHECK: jr $25                 # encoding: [0x03,0x20,0x00,0x09]        
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]