[PATCH] D18572: [AArch64] Relax branches by fusing compare with conditional branch when we can infer that source register is zero/non-zero.

[Balaram Makam via llvm-commits]

bmakam added a comment.

In http://reviews.llvm.org/D18572#388370, @t.p.northover wrote:

> > Second, this is a type of branch relaxation optimization because the branch displacement of cbz is better than a conditional branch IMHO.
>
>
> What gave you that idea? They both seem to allow imm19*4.


This was based on my observation on our hardware where I found ~4% performance improvement when we changed the following assembly

  tbnz             x15, #63, L13
  cmp              x8, #1
  b.lt             L12
  cmp              w16, #2         
  b.ne             L12
  b                L14

into:

  tbnz             x15, #63, L13
  cbz              x15, L12
  cmp              w16, #2         
  b.ne             L12
  b                L14

I might be wrong in attributing this as a result of branch displacement.


================
Comment at: lib/Target/AArch64/AArch64BranchRelaxation.cpp:483
@@ +482,3 @@
+  if (!Compare->getOperand(1).isReg() || !Compare->getOperand(2).isImm() ||
+      Compare->getOperand(2).getImm() != 1)
+    return false;
----------------
t.p.northover wrote:
> bmakam wrote:
> > t.p.northover wrote:
> > > What about "cmp reg, #0"/"b.le ..."?
> > This could be turned into a TBNZ but isn't AArch64ConditionOptimizer a better place to handle this? Although this is very similar we only fuse a compare with branch in this patch i.e.  (a>0 && a<1) -> a == 0 or (a>0 && a>= 1) -> a != 0 and so it depends on branchfolding to shape the CFG.
> The case I'm talking about is analogous though: "a > 0 && a <= 0 -> a != 0".
Ah I see, this is a valid case too. I am sorry I misread this as b.lt and was thinking a < 0 should be turned into TBNZ. 


http://reviews.llvm.org/D18572