[PATCH] D18315: [mips] MIPSR6 Compact jump support

[Vasileios Kalintiris via llvm-commits]

vkalintiris accepted this revision.
vkalintiris added a comment.
This revision is now accepted and ready to land.

LGTM with some minor inline comments. Clang-format before committing this, as I've spotted 2-3 cases with wrong indentation.


================
Comment at: lib/Target/Mips/Mips64r6InstrInfo.td:122-126
@@ -109,4 +121,7 @@
 }
-
+let isCodeGenOnly = 1 in {
+def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
+def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
+}
 //===----------------------------------------------------------------------===//
 //
----------------
Sorry, I missed the codegen-only bit.

================
Comment at: lib/Target/Mips/MipsDelaySlotFiller.cpp:582
@@ +581,3 @@
+    // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
+    // PseduoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
+    // be replaced with JRC16_MM.
----------------
s/Pseduo/Pseudo/

================
Comment at: lib/Target/Mips/MipsInstrInfo.cpp:263-270
@@ -262,7 +262,10 @@
   unsigned Opcode = I->getOpcode();
-  bool canUseShortMMBranches =
+  bool canUseShortMicroMipsCTI =
       Subtarget.inMicroMipsMode() &&
-      (Opcode == Mips::BNE || Opcode == Mips::BEQ) &&
-      I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg();
-
-  if (Subtarget.hasMips32r6() || canUseShortMMBranches) {
+      (((Opcode == Mips::BNE || Opcode == Mips::BEQ) &&
+        I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) ||
+       // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
+       // expanded to JR_MM, so they can be replaced with JRC16_MM.
+       (Opcode == Mips::JR || Opcode == Mips::PseudoReturn ||
+        Opcode == Mips::PseudoIndirectBranch));
+
----------------
There are way several conditions here. Can you replace this with a switch statement similar to the one you wrote in `CTIHasCompactMMEncoding()`?


http://reviews.llvm.org/D18315