[PATCH] D18546: Prevent X86IselLowering from merging volatile loads

[Simon Pilgrim via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM - couple of minors.

PPCISelLowering refers to SelectionDAG::isConsecutiveLoad in a comment, please can you update it so that it still makes sense?


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7257
@@ -7262,1 +7256,3 @@
+      DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1VT.getSizeInBits() / 8,
+                                         1)) {
     unsigned Align = LD1->getAlignment();
----------------
This is really horrid to grok - please can you pull out 'LD1VT.getSizeInBits() / 8' as a 'LD1Bytes' or something so we can have the call on one line?


http://reviews.llvm.org/D18546