[PATCH] D17850: Power9 - Implement byte comparison and count trailing zero instructions

[Kit Barton via llvm-commits]

kbarton accepted this revision.
kbarton added a comment.
This revision is now accepted and ready to land.

Please replace the FeatureCharCmp and FeatureCTTZ features with the more generic ISA3.0 feature (or something similar). 
With this change, this LGTM.


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Comment at: lib/Target/PowerPC/PPC.td:160
@@ -154,2 +159,3 @@
+                   "Enable count trailing zeros instructions">;
 
 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
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nemanjai wrote:
> kbarton wrote:
> > I don't see the need for adding a subtarget feature for these instructions. Why is this necessary?
> It is not necessary to add individual features for these instructions. However, it doesn't seem right to guard these by the only existing Power9 features (namely Power9Vector, Power9Altivec). Also, adding a single feature for all Power9 scalar instructions seems to break with tradition.
> Could you please suggest an alternative to defining these two features?
Based on discussions today we agreed to add a generic feature to indicate ISA3.0. The name should reflect the actual ISA version number, and not be tied to any specific chip implementation (i.e., P9). The feature definitions for P9 (e.g., P9-vector and P9-altivec) should prereq this ISA3.0 feature. Similarly, the definition of the P9 sub target should include this as well.


Repository:
  rL LLVM

http://reviews.llvm.org/D17850