[PATCH] D18566: [x86] use SSE/AVX ops for non-zero memsets (PR27100)

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 29 12:11:28 PDT 2016


On Tue, Mar 29, 2016 at 12:56 PM, Joerg Sonnenberger via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> > 2. The memset-2.ll tests look quite awkward in the way they splat the
> byte value into an XMM reg; imul isn't generally cheap.
>
> It isn't?
>

imul is usually a 3-4 cycle latency op. Given that we're going to do some
kind of vector shuffle op anyway, we could probably have just used some
other splatting shuffle and completely avoided the splat via imul?
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