[PATCH] D18315: [mips] MIPSR6 Compact jump support

[Daniel Sanders via llvm-commits]

dsanders added inline comments.

================
Comment at: lib/Target/Mips/Mips64r6InstrInfo.td:88
@@ +87,3 @@
+  bit isTerminator = 1;
+  list<Register> Defs = [AT];
+}
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vkalintiris wrote:
> I know that you probably based the definition on the 32-bit description, but do you know why we have to define $at?
I haven't dug into the details of exactly what can/can't cause it and I don't know whether it applies to this instruction or not but the explanation I was given a couple years ago was that $at may be clobbered as a result of changes made by the linker (e.g. out-of-range jumps, plt stubs, etc.).

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Comment at: test/CodeGen/Mips/llvm-ir/ret.ll:21-25
@@ +20,7 @@
+
+; FIXME: for some reason, the delay filler kicks in test ret_double_0x0 for
+;        mips64r6 but doesn't for all others. I suspect that the mthc1 is
+;        misdefined somehow, as it should be able to go in the delay slot
+;        of jr. dmtc1 fills the delay slot safely for this test, but many other
+;        cases the delay slot is unfilled. Force it off for this test.
+
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vkalintiris wrote:
> MTHC1 has *unmodeled side-effects* and the DSF bails out on these instructions (see Filler::terminateSearch). Can you update the comment to reflect this?
MTHC1 shouldn't have side-effects, it looks like tablegen is inferring it from the lack of a codegen pattern.


http://reviews.llvm.org/D18315