[llvm] r264607 - CodeGen: Correct specification of PHI nodes

[Matthias Braun via llvm-commits]

Author: matze
Date: Mon Mar 28 13:18:41 2016
New Revision: 264607

URL: http://llvm.org/viewvc/llvm-project?rev=264607&view=rev
Log:
CodeGen: Correct specification of PHI nodes

They do have a def machine operand.

Fixing the definition is necessary for an upcoming patch.

Differential Revision: http://reviews.llvm.org/D18384

Modified:
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=264607&r1=264606&r2=264607&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Mon Mar 28 13:18:41 2016
@@ -773,7 +773,7 @@ class InstrInfo {
 let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
     Namespace = "TargetOpcode" in {
 def PHI : Instruction {
-  let OutOperandList = (outs);
+  let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
   let AsmString = "PHINODE";
 }

Modified: llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll?rev=264607&r1=264606&r2=264607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll Mon Mar 28 13:18:41 2016
@@ -138,11 +138,11 @@ exit:
 ; SI: BB#4:
 ; SI: buffer_store_dword
 ; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
-; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
+; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
 
 ; SI: BB3_5:
 ; SI: s_or_b64 exec, exec, [[ORNEG2]]
-; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
+; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
 ; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
 ; SI: s_cbranch_execnz BB3_3