[llvm] r264403 - [X86][SSE] Don't duplicate Lower256IntArith functionality in LowerShift. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 25 07:17:54 PDT 2016
Author: rksimon
Date: Fri Mar 25 09:17:54 2016
New Revision: 264403
URL: http://llvm.org/viewvc/llvm-project?rev=264403&view=rev
Log:
[X86][SSE] Don't duplicate Lower256IntArith functionality in LowerShift. NFC.
LowerShift was using the same code as Lower256IntArith to split 256-bit vectors into 2 x 128-bit vectors, so now we just call Lower256IntArith.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=264403&r1=264402&r2=264403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Mar 25 09:17:54 2016
@@ -19897,26 +19897,8 @@ static SDValue LowerShift(SDValue Op, co
}
// Decompose 256-bit shifts into smaller 128-bit shifts.
- if (VT.is256BitVector()) {
- unsigned NumElems = VT.getVectorNumElements();
- MVT EltVT = VT.getVectorElementType();
- MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
-
- // Extract the two vectors
- SDValue V1 = extract128BitVector(R, 0, DAG, dl);
- SDValue V2 = extract128BitVector(R, NumElems / 2, DAG, dl);
-
- // Recreate the shift amount vectors
- SDValue Amt1 = extract128BitVector(Amt, 0, DAG, dl);
- SDValue Amt2 = extract128BitVector(Amt, NumElems / 2, DAG, dl);
-
- // Issue new vector shifts for the smaller types
- V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
- V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
-
- // Concatenate the result back
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
- }
+ if (VT.is256BitVector())
+ return Lower256IntArith(Op, DAG);
return SDValue();
}
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