[llvm] r264370 - ARM: fix optimised division on WoA

[Saleem Abdulrasool via llvm-commits]

Author: compnerd
Date: Thu Mar 24 19:34:11 2016
New Revision: 264370

URL: http://llvm.org/viewvc/llvm-project?rev=264370&view=rev
Log:
ARM: fix optimised division on WoA

We did not have an explicit branch to the continuation BB.  When the check was
hoisted, this could permit control follow to fall through into the division
trap.  Add the explicit branch to the continuation basic block to ensure that
code execution is correct.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/Windows/division.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=264370&r1=264369&r2=264370&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Mar 24 19:34:11 2016
@@ -8064,6 +8064,7 @@ ARMTargetLowering::EmitLowered__dbzchk(M
   BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ))
       .addReg(MI->getOperand(0).getReg())
       .addMBB(TrapBB);
+  AddDefaultPred(BuildMI(*MBB, MI, DL, TII->get(ARM::t2B)).addMBB(ContBB));
   MBB->addSuccessor(ContBB);
 
   MI->eraseFromParent();

Modified: llvm/trunk/test/CodeGen/ARM/Windows/division.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/Windows/division.ll?rev=264370&r1=264369&r2=264370&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/Windows/division.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/Windows/division.ll Thu Mar 24 19:34:11 2016
@@ -9,8 +9,9 @@ entry:
 
 ; CHECK-LABEL: sdiv32:
 ; CHECK: cbz r0
-; CHECK: bl __rt_sdiv
+; CHECK: b
 ; CHECK: udf.w #249
+; CHECK: bl __rt_sdiv
 
 define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
 entry:
@@ -20,8 +21,9 @@ entry:
 
 ; CHECK-LABEL: udiv32:
 ; CHECK: cbz r0
-; CHECK: bl __rt_udiv
+; CHECK: b
 ; CHECK: udf.w #249
+; CHECK: bl __rt_udiv
 
 define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -32,8 +34,9 @@ entry:
 ; CHECK-LABEL: sdiv64:
 ; CHECK: orr.w r12, r0, r1
 ; CHECK-NEXT: cbz r12
-; CHECK: bl __rt_sdiv64
+; CHECK: b
 ; CHECK: udf.w #249
+; CHECK: bl __rt_sdiv64
 
 define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -44,6 +47,32 @@ entry:
 ; CHECK-LABEL: udiv64:
 ; CHECK: orr.w r12, r0, r1
 ; CHECK-NEXT: cbz r12
+; CHECK: b
+; CHECK: udf.w #249
 ; CHECK: bl __rt_udiv64
+
+declare arm_aapcs_vfpcc i32 @g(...)
+
+define arm_aapcs_vfpcc i32 @f(i32 %b, i32 %d) #0 {
+entry:
+  %tobool = icmp eq i32 %b, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %call = tail call arm_aapcs_vfpcc i32 bitcast (i32 (...)* @g to i32 ()*)()
+  %rem = urem i32 %call, %d
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %rem, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+; CHECK-LABEL: f:
+; CHECK: cbz r0,
+; CHECK: cbz r4,
+; CHECK: b
 ; CHECK: udf.w #249
 
+attributes #0 = { optsize }
+