[PATCH] D18356: [selectionDAG][atomics] Add sign extension handling to atom cmp and swap

Simon Dardis via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 24 04:38:08 PDT 2016


sdardis added a comment.

This doesn't fix the 32 bit on 64 bit case.

For 16 on 32bit:

  Legalizing: t22: i32,i32,ch = AtomicCmpSwapWithSuccess<Volatile LDST2[%addr]> t11, t2, t4, t6
   ... replacing: t22: i32,i32,ch = AtomicCmpSwapWithSuccess<Volatile LDST2[%addr]> t11, t2, t4, t6
       with:      t27: i32 = AssertSext t25, ValueType:ch:i16
        and:      t30: i32 = setcc t27, t28, seteq:ch
        and:      t25: i32,ch = AtomicCmpSwap<Volatile LDST2[%addr]> t11, t2, t4, t6

Which is what is required. But for 32 on  64bit I'm getting:

  Legalizing: t27: i32,i32,ch = AtomicCmpSwapWithSuccess<Volatile LDST4[%addr]> t18, t2, t7, t15
   ... replacing: t27: i32,i32,ch = AtomicCmpSwapWithSuccess<Volatile LDST4[%addr]> t18, t2, t7, t15
       with:      t30: i32,ch = AtomicCmpSwap<Volatile LDST4[%addr]> t18, t2, t7, t15
        and:      t32: i32 = setcc t30, t7, seteq:ch
        and:      t30: i32,ch = AtomicCmpSwap<Volatile LDST4[%addr]> t18, t2, t7, t15

This is after adding:

  if (Subtarget.isGP64bit()) {
    AddPromotedToType(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, MVT::i64);
    AddPromotedToType(ISD::ATOMIC_CMP_SWAP, MVT::i32, MVT::i64);
  }

To MipsISelLowering.cpp. Any suggestions?


http://reviews.llvm.org/D18356





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