[llvm] r264245 - [mips][microMIPS] Fix for "Cannot copy registers" assertion

Hrvoje Varga via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 23 23:05:36 PDT 2016 

Author: hvarga
Date: Thu Mar 24 01:05:35 2016
New Revision: 264245

URL: http://llvm.org/viewvc/llvm-project?rev=264245&view=rev
Log:
[mips][microMIPS] Fix for "Cannot copy registers" assertion
Differential Revision: http://reviews.llvm.org/D17068

Modified:
    llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
    llvm/trunk/test/CodeGen/Mips/micromips-addiu.ll
    llvm/trunk/test/CodeGen/Mips/micromips-andi.ll
    llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll

Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=264245&r1=264244&r2=264245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Mar 24 01:05:35 2016
@@ -49,7 +49,7 @@ def MicroMipsMemGPRMM16AsmOperand : AsmO
 
 class mem_mm_4_generic : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPRMM16, simm4);
+  let MIOperandInfo = (ops ptr_rc, simm4);
   let OperandType = "OPERAND_MEMORY";
   let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
 }
@@ -75,7 +75,7 @@ def MicroMipsMemSPAsmOperand : AsmOperan
 
 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
+  let MIOperandInfo = (ops ptr_rc:$base, simm5:$offset);
   let OperandType = "OPERAND_MEMORY";
   let ParserMatchClass = MicroMipsMemSPAsmOperand;
   let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
@@ -90,7 +90,7 @@ def mem_mm_gp_imm7_lsl2 : Operand<i32> {
 
 def mem_mm_9 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, simm9);
+  let MIOperandInfo = (ops ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -98,7 +98,7 @@ def mem_mm_9 : Operand<i32> {
 
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, simm12);
+  let MIOperandInfo = (ops ptr_rc, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -106,7 +106,7 @@ def mem_mm_12 : Operand<i32> {
 
 def mem_mm_16 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, simm16);
+  let MIOperandInfo = (ops ptr_rc, simm16);
   let EncoderMethod = "getMemEncodingMMImm16";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -122,7 +122,7 @@ def MipsMemUimm4AsmOperand : AsmOperandC
 
 def mem_mm_4sp : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, uimm8);
+  let MIOperandInfo = (ops ptr_rc, uimm8);
   let EncoderMethod = "getMemEncodingMMImm4sp";
   let ParserMatchClass = MipsMemUimm4AsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -203,7 +203,7 @@ def movep_regpair : Operand<i32> {
   let ParserMatchClass = MovePRegPairAsmOperand;
   let PrintMethod = "printRegisterList";
   let DecoderMethod = "DecodeMovePRegPair";
-  let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
+  let MIOperandInfo = (ops ptr_rc, ptr_rc);
 }
 
 class MovePMM16<string opstr, RegisterOperand RO> :
@@ -224,7 +224,7 @@ def regpair : Operand<i32> {
   let ParserMatchClass = RegPairAsmOperand;
   let PrintMethod = "printRegisterPair";
   let DecoderMethod = "DecodeRegPairOperand";
-  let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
+  let MIOperandInfo = (ops ptr_rc, ptr_rc);
 }
 
 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,

Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp?rev=264245&r1=264244&r2=264245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp Thu Mar 24 01:05:35 2016
@@ -42,7 +42,9 @@ unsigned MipsFunctionInfo::getGlobalBase
       STI.inMips16Mode()
           ? &Mips::CPU16RegsRegClass
           : STI.inMicroMipsMode()
-                ? &Mips::GPRMM16RegClass
+                ? STI.hasMips64()
+                      ? &Mips::GPRMM16_64RegClass
+                      : &Mips::GPRMM16RegClass
                 : static_cast<const MipsTargetMachine &>(MF.getTarget())
                           .getABI()
                           .IsN64()

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=264245&r1=264244&r2=264245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Thu Mar 24 01:05:35 2016
@@ -330,6 +330,12 @@ def GPR64 : RegisterClass<"Mips", [i64],
   // Reserved
   K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
 
+def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add
+  // Callee save
+  S0_64, S1_64,
+  // Return Values and Arguments
+  V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>;
+
 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
   // Return Values and Arguments
   V0, V1, A0, A1, A2, A3,

Modified: llvm/trunk/test/CodeGen/Mips/micromips-addiu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-addiu.ll?rev=264245&r1=264244&r2=264245&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-addiu.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-addiu.ll Thu Mar 24 01:05:35 2016
@@ -1,5 +1,8 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @x = global i32 65504, align 4
 @y = global i32 60929, align 4

Modified: llvm/trunk/test/CodeGen/Mips/micromips-andi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-andi.ll?rev=264245&r1=264244&r2=264245&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-andi.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-andi.ll Thu Mar 24 01:05:35 2016
@@ -1,5 +1,8 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @x = global i32 65504, align 4
 @y = global i32 60929, align 4

Modified: llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll?rev=264245&r1=264244&r2=264245&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll Thu Mar 24 01:05:35 2016
@@ -1,5 +1,8 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @g = external global i32

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