[PATCH] D18049: AMDGPU i16 implementation

[Matt Arsenault via llvm-commits]

arsenm added inline comments.

================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:2022-2031
@@ -1944,2 +2021,12 @@
 
+  if (VT == MVT::i16) {
+    SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Store->getValue());
+
+    return DAG.getTruncStore(Store->getChain(), DL,
+                             Ext,
+                             Store->getBasePtr(),
+                             MVT::i16,
+                             Store->getMemOperand());
+  }
+
   if (VT == MVT::i1) {
----------------
tstellarAMD wrote:
> We do we need to custom lower i16 stores?  Can't we just mark then as promote?
Load/store promote expects an equal size type for a bitcast promote. This is the same problem that i1 has, so it should follow that example


Repository:
  rL LLVM

http://reviews.llvm.org/D18049