[llvm] r264165 - Replace a string comparison in ARMSubtarget.h with a tablegen entry in ARM.td (NFC)
Artyom Skrobov via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 23 09:18:14 PDT 2016
Author: askrobov
Date: Wed Mar 23 11:18:13 2016
New Revision: 264165
URL: http://llvm.org/viewvc/llvm-project?rev=264165&view=rev
Log:
Replace a string comparison in ARMSubtarget.h with a tablegen entry in ARM.td (NFC)
Reviewers: rengolin, t.p.northover
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D18393
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=264165&r1=264164&r2=264165&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Wed Mar 23 11:18:13 2016
@@ -278,6 +278,8 @@ def ProcR5 : SubtargetFeature<"r5",
def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
"Cortex-R7 ARM processors", []>;
+def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
+ "Cortex-M3 ARM processors", []>;
//===----------------------------------------------------------------------===//
// ARM schedules.
@@ -641,8 +643,8 @@ def : ProcessorModel<"cortex-r8", Cort
FeatureAvoidPartialCPSR,
FeatureT2XtPk]>;
-def : ProcNoItin<"cortex-m3", [ARMv7m]>;
-def : ProcNoItin<"sc300", [ARMv7m]>;
+def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
+def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
def : ProcNoItin<"cortex-m4", [ARMv7em,
FeatureVFP4,
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=264165&r1=264164&r2=264165&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Mar 23 11:18:13 2016
@@ -43,8 +43,9 @@ class ARMSubtarget : public ARMGenSubtar
protected:
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
- CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA32, CortexA35,
- CortexA53, CortexA57, CortexA72, Krait, Swift, ExynosM1
+ CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,
+ CortexA32, CortexA35, CortexA53, CortexA57, CortexA72,
+ Krait, Swift, ExynosM1
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass
@@ -334,7 +335,7 @@ public:
bool isCortexA9() const { return ARMProcFamily == CortexA9; }
bool isCortexA15() const { return ARMProcFamily == CortexA15; }
bool isSwift() const { return ARMProcFamily == Swift; }
- bool isCortexM3() const { return CPUString == "cortex-m3"; }
+ bool isCortexM3() const { return ARMProcFamily == CortexM3; }
bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
bool isCortexR5() const { return ARMProcFamily == CortexR5; }
bool isKrait() const { return ARMProcFamily == Krait; }
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