[PATCH] D18384: CodeGen: Correct specification of PHI nodes
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 22 20:35:46 PDT 2016
MatzeB created this revision.
MatzeB added reviewers: tstellarAMD, arsenm.
MatzeB added subscribers: llvm-commits, qcolombet.
MatzeB set the repository for this revision to rL LLVM.
Herald added a subscriber: mcrosier.
They do have a def machine operand.
Fixing the definition is necessary for an upcoming patch.
Repository:
rL LLVM
http://reviews.llvm.org/D18384
Files:
include/llvm/Target/Target.td
test/CodeGen/AMDGPU/valu-i1.ll
Index: test/CodeGen/AMDGPU/valu-i1.ll
===================================================================
--- test/CodeGen/AMDGPU/valu-i1.ll
+++ test/CodeGen/AMDGPU/valu-i1.ll
@@ -138,11 +138,11 @@
; SI: BB#4:
; SI: buffer_store_dword
; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
-; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
+; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
; SI: BB3_5:
; SI: s_or_b64 exec, exec, [[ORNEG2]]
-; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
+; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
; SI: s_cbranch_execnz BB3_3
Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -773,7 +773,7 @@
let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
Namespace = "TargetOpcode" in {
def PHI : Instruction {
- let OutOperandList = (outs);
+ let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
let AsmString = "PHINODE";
}
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