[PATCH] D14807: AMDGPU: Implement SIRegisterInfo::getRegPressureSetScore()
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 22 18:33:53 PDT 2016
tstellarAMD updated this revision to Diff 51375.
tstellarAMD added a comment.
Rebased and address some review comments. However, register usage is now worse
with this patch.
http://reviews.llvm.org/D14807
Files:
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/SIRegisterInfo.h
Index: lib/Target/AMDGPU/SIRegisterInfo.h
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.h
+++ lib/Target/AMDGPU/SIRegisterInfo.h
@@ -51,6 +51,9 @@
unsigned getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const override;
+ unsigned getRegPressureSetScore(const MachineFunction &MF,
+ unsigned PSetID) const override;
+
bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -187,6 +187,25 @@
return VGPRLimit;
}
+unsigned SIRegisterInfo::getRegPressureSetScore(const MachineFunction &MF,
+ unsigned PSetID) const {
+
+ if (SGPRPressureSets.test(PSetID)) {
+ if (VGPRPressureSets.test(PSetID)) {
+ // If a pressure set contains vgprs and sgprs then we prefer incresing
+ // its pressure over regular register classes. This has the hightest
+ // score.
+ return 2;
+ }
+ // If this is an SGPR pressure set we prefer increasing its pressure
+ // over VGPR pressure sets.
+ return 1;
+ }
+
+ // VGPRS.
+ return 0;
+}
+
bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
return Fn.getFrameInfo()->hasStackObjects();
}
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