[llvm] r263981 - [Hexagon] Add handling fixups and instruction relaxation
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 21 13:27:18 PDT 2016
Author: kparzysz
Date: Mon Mar 21 15:27:17 2016
New Revision: 263981
URL: http://llvm.org/viewvc/llvm-project?rev=263981&view=rev
Log:
[Hexagon] Add handling fixups and instruction relaxation
Added:
llvm/trunk/test/MC/Hexagon/fixups.s
Modified:
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=263981&r1=263980&r2=263981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Mon Mar 21 15:27:17 2016
@@ -22,11 +22,16 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/TargetRegistry.h"
+#include <sstream>
+
using namespace llvm;
using namespace Hexagon;
#define DEBUG_TYPE "hexagon-asm-backend"
+static cl::opt<bool> DisableFixup
+ ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
+
namespace {
class HexagonAsmBackend : public MCAsmBackend {
@@ -37,7 +42,7 @@ class HexagonAsmBackend : public MCAsmBa
std::unique_ptr <MCInst *> RelaxTarget;
MCInst * Extender;
public:
- HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) :
+ HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) :
OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),
Extender(nullptr) {}
@@ -63,118 +68,438 @@ public:
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
- // This table *must* be in same the order of fixup_* kinds in
- // HexagonFixupKinds.h.
- //
- // namei offset bits flags
- {"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_LO16", 0, 32, 0},
- {"fixup_Hexagon_HI16", 0, 32, 0},
- {"fixup_Hexagon_32", 0, 32, 0},
- {"fixup_Hexagon_16", 0, 32, 0},
- {"fixup_Hexagon_8", 0, 32, 0},
- {"fixup_Hexagon_GPREL16_0", 0, 32, 0},
- {"fixup_Hexagon_GPREL16_1", 0, 32, 0},
- {"fixup_Hexagon_GPREL16_2", 0, 32, 0},
- {"fixup_Hexagon_GPREL16_3", 0, 32, 0},
- {"fixup_Hexagon_HL16", 0, 32, 0},
- {"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_16_X", 0, 32, 0},
- {"fixup_Hexagon_12_X", 0, 32, 0},
- {"fixup_Hexagon_11_X", 0, 32, 0},
- {"fixup_Hexagon_10_X", 0, 32, 0},
- {"fixup_Hexagon_9_X", 0, 32, 0},
- {"fixup_Hexagon_8_X", 0, 32, 0},
- {"fixup_Hexagon_7_X", 0, 32, 0},
- {"fixup_Hexagon_6_X", 0, 32, 0},
- {"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_COPY", 0, 32, 0},
- {"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
- {"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
- {"fixup_Hexagon_RELATIVE", 0, 32, 0},
- {"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
- {"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
- {"fixup_Hexagon_GOTREL_32", 0, 32, 0},
- {"fixup_Hexagon_GOT_LO16", 0, 32, 0},
- {"fixup_Hexagon_GOT_HI16", 0, 32, 0},
- {"fixup_Hexagon_GOT_32", 0, 32, 0},
- {"fixup_Hexagon_GOT_16", 0, 32, 0},
- {"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_32", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_16", 0, 32, 0},
- {"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
- {"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
- {"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
- {"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
- {"fixup_Hexagon_IE_LO16", 0, 32, 0},
- {"fixup_Hexagon_IE_HI16", 0, 32, 0},
- {"fixup_Hexagon_IE_32", 0, 32, 0},
- {"fixup_Hexagon_IE_16", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
- {"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
- {"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
- {"fixup_Hexagon_TPREL_32", 0, 32, 0},
- {"fixup_Hexagon_TPREL_16", 0, 32, 0},
- {"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
- {"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
- {"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_GOT_16_X", 0, 32, 0},
- {"fixup_Hexagon_GOT_11_X", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
- {"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
- {"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
- {"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
- {"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
- {"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_IE_16_X", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
- {"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
- {"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
- {"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
- {"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
+ // This table *must* be in same the order of fixup_* kinds in
+ // HexagonFixupKinds.h.
+ //
+ // namei offset bits flags
+ { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_32", 0, 32, 0 },
+ { "fixup_Hexagon_16", 0, 32, 0 },
+ { "fixup_Hexagon_8", 0, 32, 0 },
+ { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
+ { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
+ { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
+ { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
+ { "fixup_Hexagon_HL16", 0, 32, 0 },
+ { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_12_X", 0, 32, 0 },
+ { "fixup_Hexagon_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_10_X", 0, 32, 0 },
+ { "fixup_Hexagon_9_X", 0, 32, 0 },
+ { "fixup_Hexagon_8_X", 0, 32, 0 },
+ { "fixup_Hexagon_7_X", 0, 32, 0 },
+ { "fixup_Hexagon_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_COPY", 0, 32, 0 },
+ { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
+ { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
+ { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
+ { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_32", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_16", 0, 32, 0 },
+ { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
+ { "fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
+ { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
+ { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_IE_32", 0, 32, 0 },
+ { "fixup_Hexagon_IE_16", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
+ { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
+ { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }
+ };
- if (Kind < FirstTargetFixupKind) {
+ if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
- }
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
}
- void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
- unsigned /*DataSize*/, uint64_t /*Value*/,
- bool /*IsPCRel*/) const override {
- return;
+ /// processFixupValue - Target hook to adjust the literal value of a fixup
+ /// if necessary. IsResolved signals whether the caller believes a relocation
+ /// is needed; the target can modify the value. The default does nothing.
+ void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
+ const MCFixup &Fixup, const MCFragment *DF,
+ const MCValue &Target, uint64_t &Value,
+ bool &IsResolved) override {
+ MCFixupKind Kind = Fixup.getKind();
+
+ switch((unsigned)Kind) {
+ default:
+ llvm_unreachable("Unknown Fixup Kind!");
+
+ case fixup_Hexagon_LO16:
+ case fixup_Hexagon_HI16:
+ case fixup_Hexagon_16:
+ case fixup_Hexagon_8:
+ case fixup_Hexagon_GPREL16_0:
+ case fixup_Hexagon_GPREL16_1:
+ case fixup_Hexagon_GPREL16_2:
+ case fixup_Hexagon_GPREL16_3:
+ case fixup_Hexagon_HL16:
+ case fixup_Hexagon_32_6_X:
+ case fixup_Hexagon_16_X:
+ case fixup_Hexagon_12_X:
+ case fixup_Hexagon_11_X:
+ case fixup_Hexagon_10_X:
+ case fixup_Hexagon_9_X:
+ case fixup_Hexagon_8_X:
+ case fixup_Hexagon_7_X:
+ case fixup_Hexagon_6_X:
+ case fixup_Hexagon_COPY:
+ case fixup_Hexagon_GLOB_DAT:
+ case fixup_Hexagon_JMP_SLOT:
+ case fixup_Hexagon_RELATIVE:
+ case fixup_Hexagon_PLT_B22_PCREL:
+ case fixup_Hexagon_GOTREL_LO16:
+ case fixup_Hexagon_GOTREL_HI16:
+ case fixup_Hexagon_GOTREL_32:
+ case fixup_Hexagon_GOT_LO16:
+ case fixup_Hexagon_GOT_HI16:
+ case fixup_Hexagon_GOT_32:
+ case fixup_Hexagon_GOT_16:
+ case fixup_Hexagon_DTPMOD_32:
+ case fixup_Hexagon_DTPREL_LO16:
+ case fixup_Hexagon_DTPREL_HI16:
+ case fixup_Hexagon_DTPREL_32:
+ case fixup_Hexagon_DTPREL_16:
+ case fixup_Hexagon_GD_PLT_B22_PCREL:
+ case fixup_Hexagon_LD_PLT_B22_PCREL:
+ case fixup_Hexagon_GD_GOT_LO16:
+ case fixup_Hexagon_GD_GOT_HI16:
+ case fixup_Hexagon_GD_GOT_32:
+ case fixup_Hexagon_GD_GOT_16:
+ case fixup_Hexagon_LD_GOT_LO16:
+ case fixup_Hexagon_LD_GOT_HI16:
+ case fixup_Hexagon_LD_GOT_32:
+ case fixup_Hexagon_LD_GOT_16:
+ case fixup_Hexagon_IE_LO16:
+ case fixup_Hexagon_IE_HI16:
+ case fixup_Hexagon_IE_32:
+ case fixup_Hexagon_IE_16:
+ case fixup_Hexagon_IE_GOT_LO16:
+ case fixup_Hexagon_IE_GOT_HI16:
+ case fixup_Hexagon_IE_GOT_32:
+ case fixup_Hexagon_IE_GOT_16:
+ case fixup_Hexagon_TPREL_LO16:
+ case fixup_Hexagon_TPREL_HI16:
+ case fixup_Hexagon_TPREL_32:
+ case fixup_Hexagon_TPREL_16:
+ case fixup_Hexagon_GOTREL_32_6_X:
+ case fixup_Hexagon_GOTREL_16_X:
+ case fixup_Hexagon_GOTREL_11_X:
+ case fixup_Hexagon_GOT_32_6_X:
+ case fixup_Hexagon_GOT_16_X:
+ case fixup_Hexagon_GOT_11_X:
+ case fixup_Hexagon_DTPREL_32_6_X:
+ case fixup_Hexagon_DTPREL_16_X:
+ case fixup_Hexagon_DTPREL_11_X:
+ case fixup_Hexagon_GD_GOT_32_6_X:
+ case fixup_Hexagon_GD_GOT_16_X:
+ case fixup_Hexagon_GD_GOT_11_X:
+ case fixup_Hexagon_LD_GOT_32_6_X:
+ case fixup_Hexagon_LD_GOT_16_X:
+ case fixup_Hexagon_LD_GOT_11_X:
+ case fixup_Hexagon_IE_32_6_X:
+ case fixup_Hexagon_IE_16_X:
+ case fixup_Hexagon_IE_GOT_32_6_X:
+ case fixup_Hexagon_IE_GOT_16_X:
+ case fixup_Hexagon_IE_GOT_11_X:
+ case fixup_Hexagon_TPREL_32_6_X:
+ case fixup_Hexagon_TPREL_16_X:
+ case fixup_Hexagon_TPREL_11_X:
+ case fixup_Hexagon_32_PCREL:
+ case fixup_Hexagon_6_PCREL_X:
+ case fixup_Hexagon_23_REG:
+ // These relocations should always have a relocation recorded
+ IsResolved = false;
+ return;
+
+ case fixup_Hexagon_B22_PCREL:
+ //IsResolved = false;
+ break;
+
+ case fixup_Hexagon_B13_PCREL:
+ case fixup_Hexagon_B13_PCREL_X:
+ case fixup_Hexagon_B32_PCREL_X:
+ case fixup_Hexagon_B22_PCREL_X:
+ case fixup_Hexagon_B15_PCREL:
+ case fixup_Hexagon_B15_PCREL_X:
+ case fixup_Hexagon_B9_PCREL:
+ case fixup_Hexagon_B9_PCREL_X:
+ case fixup_Hexagon_B7_PCREL:
+ case fixup_Hexagon_B7_PCREL_X:
+ if (DisableFixup)
+ IsResolved = false;
+ break;
+
+ case FK_Data_1:
+ case FK_Data_2:
+ case FK_Data_4:
+ case FK_PCRel_4:
+ case fixup_Hexagon_32:
+ // Leave these relocations alone as they are used for EH.
+ return;
+ }
+ }
+
+ /// getFixupKindNumBytes - The number of bytes the fixup may change.
+ static unsigned getFixupKindNumBytes(unsigned Kind) {
+ switch (Kind) {
+ default:
+ return 0;
+
+ case FK_Data_1:
+ return 1;
+ case FK_Data_2:
+ return 2;
+ case FK_Data_4: // this later gets mapped to R_HEX_32
+ case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
+ case fixup_Hexagon_32:
+ case fixup_Hexagon_B32_PCREL_X:
+ case fixup_Hexagon_B22_PCREL:
+ case fixup_Hexagon_B22_PCREL_X:
+ case fixup_Hexagon_B15_PCREL:
+ case fixup_Hexagon_B15_PCREL_X:
+ case fixup_Hexagon_B13_PCREL:
+ case fixup_Hexagon_B13_PCREL_X:
+ case fixup_Hexagon_B9_PCREL:
+ case fixup_Hexagon_B9_PCREL_X:
+ case fixup_Hexagon_B7_PCREL:
+ case fixup_Hexagon_B7_PCREL_X:
+ return 4;
+ }
+ }
+
+ // Make up for left shift when encoding the operand.
+ static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) {
+ switch((unsigned)Kind) {
+ default:
+ break;
+
+ case fixup_Hexagon_B7_PCREL:
+ case fixup_Hexagon_B9_PCREL:
+ case fixup_Hexagon_B13_PCREL:
+ case fixup_Hexagon_B15_PCREL:
+ case fixup_Hexagon_B22_PCREL:
+ Value >>= 2;
+ break;
+
+ case fixup_Hexagon_B7_PCREL_X:
+ case fixup_Hexagon_B9_PCREL_X:
+ case fixup_Hexagon_B13_PCREL_X:
+ case fixup_Hexagon_B15_PCREL_X:
+ case fixup_Hexagon_B22_PCREL_X:
+ Value &= 0x3f;
+ break;
+
+ case fixup_Hexagon_B32_PCREL_X:
+ Value >>= 6;
+ break;
+ }
+ return (Value);
+ }
+
+ void HandleFixupError(const int bits, const int align_bits,
+ const int64_t FixupValue, const char *fixupStr) const {
+ // Error: value 1124 out of range: -1024-1023 when resolving
+ // symbol in file xprtsock.S
+ const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
+ const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
+ std::stringstream errStr;
+ errStr << "\nError: value " <<
+ FixupValue <<
+ " out of range: " <<
+ IntMin.getSExtValue() <<
+ "-" <<
+ IntMax.getSExtValue() <<
+ " when resolving " <<
+ fixupStr <<
+ " fixup\n";
+ llvm_unreachable(errStr.str().c_str());
+ }
+
+ /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
+ /// data fragment, at the offset specified by the fixup and following the
+ /// fixup kind as appropriate.
+ void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
+ uint64_t FixupValue, bool IsPCRel) const override {
+
+ // When FixupValue is 0 the relocation is external and there
+ // is nothing for us to do.
+ if (!FixupValue) return;
+
+ MCFixupKind Kind = Fixup.getKind();
+ uint64_t Value;
+ uint32_t InstMask;
+ uint32_t Reloc;
+
+ // LLVM gives us an encoded value, we have to convert it back
+ // to a real offset before we can use it.
+ uint32_t Offset = Fixup.getOffset();
+ unsigned NumBytes = getFixupKindNumBytes(Kind);
+ assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
+ char* InstAddr = Data + Offset;
+
+ Value = adjustFixupValue(Kind, FixupValue);
+ if(!Value)
+ return;
+ signed sValue = (signed)Value;
+
+ switch((unsigned)Kind) {
+ default:
+ return;
+
+ case fixup_Hexagon_B7_PCREL:
+ if (!(isIntN(7, sValue)))
+ HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
+ case fixup_Hexagon_B7_PCREL_X:
+ InstMask = 0x00001f18; // Word32_B7
+ Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
+ ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
+ break;
+
+ case fixup_Hexagon_B9_PCREL:
+ if (!(isIntN(9, sValue)))
+ HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
+ case fixup_Hexagon_B9_PCREL_X:
+ InstMask = 0x003000fe; // Word32_B9
+ Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
+ ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
+ break;
+
+ // Since the existing branches that use this relocation cannot be
+ // extended, they should only be fixed up if the target is within range.
+ case fixup_Hexagon_B13_PCREL:
+ if (!(isIntN(13, sValue)))
+ HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
+ case fixup_Hexagon_B13_PCREL_X:
+ InstMask = 0x00202ffe; // Word32_B13
+ Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
+ (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
+ ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
+ break;
+
+ case fixup_Hexagon_B15_PCREL:
+ if (!(isIntN(15, sValue)))
+ HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
+ case fixup_Hexagon_B15_PCREL_X:
+ InstMask = 0x00df20fe; // Word32_B15
+ Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
+ (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
+ (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
+ ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
+ break;
+
+ case fixup_Hexagon_B22_PCREL:
+ if (!(isIntN(22, sValue)))
+ HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
+ case fixup_Hexagon_B22_PCREL_X:
+ InstMask = 0x01ff3ffe; // Word32_B22
+ Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
+ ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
+ break;
+
+ case fixup_Hexagon_B32_PCREL_X:
+ InstMask = 0x0fff3fff; // Word32_X26
+ Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
+ (Value & 0x3fff); // Value 13-0 = Target 13-0
+ break;
+
+ case FK_Data_1:
+ case FK_Data_2:
+ case FK_Data_4:
+ case fixup_Hexagon_32:
+ InstMask = 0xffffffff; // Word32
+ Reloc = Value;
+ break;
+ }
+
+ DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" <<
+ (unsigned)Kind << ")\n");
+ DEBUG(uint32_t OldData = 0;
+ for (unsigned i = 0; i < NumBytes; i++)
+ OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
+ dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) <<
+ ": AValue=0x"; dbgs().write_hex(FixupValue) <<
+ ": Offset=" << Offset <<
+ ": Size=" << DataSize <<
+ ": OInst=0x"; dbgs().write_hex(OldData) <<
+ ": Reloc=0x"; dbgs().write_hex(Reloc););
+
+ // For each byte of the fragment that the fixup touches, mask in the
+ // bits from the fixup value. The Value has been "split up" into the
+ // appropriate bitfields above.
+ for (unsigned i = 0; i < NumBytes; i++){
+ InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
+ InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
+ }
+
+ DEBUG(uint32_t NewData = 0;
+ for (unsigned i = 0; i < NumBytes; i++)
+ NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
+ dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
}
bool isInstRelaxable(MCInst const &HMI) const {
@@ -182,12 +507,20 @@ public:
bool Relaxable = false;
// Branches and loop-setup insns are handled as necessary by relaxation.
if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
+ (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
+ HexagonII::TypeCOMPOUND &&
+ MCID.isBranch()) ||
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
MCID.isBranch()) ||
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
HMI.getOpcode() != Hexagon::C4_addipc))
- if (HexagonMCInstrInfo::isExtendable(*MCII, HMI))
+ if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
Relaxable = true;
+ MCOperand const &Operand =
+ HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI));
+ if (HexagonMCInstrInfo::mustNotExtend(*Operand.getExpr()))
+ Relaxable = false;
+ }
return Relaxable;
}
@@ -202,8 +535,14 @@ public:
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
auto const &Inst = *I.getInst();
if (!PreviousIsExtender) {
- if (isInstRelaxable(Inst))
- return true;
+ if (HexagonMCInstrInfo::isDuplex(*MCII, Inst)) {
+ if (isInstRelaxable(*Inst.getOperand(0).getInst()) ||
+ isInstRelaxable(*Inst.getOperand(1).getInst()))
+ return true;
+ } else {
+ if (isInstRelaxable(Inst))
+ return true;
+ }
}
PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
}
@@ -222,6 +561,9 @@ public:
*RelaxTarget = nullptr;
MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
+ bool Relaxable = isInstRelaxable(MCI);
+ if (Relaxable == false)
+ return false;
// If we cannot resolve the fixup value, it requires relaxation.
if (!Resolved) {
switch ((unsigned)Fixup.getKind()) {
@@ -247,9 +589,6 @@ public:
}
}
}
- bool Relaxable = isInstRelaxable(MCI);
- if (Relaxable == false)
- return false;
MCFixupKind Kind = Fixup.getKind();
int64_t sValue = Value;
Added: llvm/trunk/test/MC/Hexagon/fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/fixups.s?rev=263981&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/fixups.s (added)
+++ llvm/trunk/test/MC/Hexagon/fixups.s Mon Mar 21 15:27:17 2016
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+ .text
+# CHECK-LABEL: 0:
+# CHECK: 2442e106
+# CHECK: if (!cmp.eq(r1.new, #1)) jump:t 0xc
+ {
+ r1 = zxth(r2)
+ if (!cmp.eq(r1.new, #1)) jump:t .L1
+ }
+ nop
+.L1:
+ .org 0x10
+# CHECK-LABEL: 10:
+# CHECK: 00004020
+# CHECK: immext(#2048)
+# CHECK: 2442e118
+# CHECK: if (!cmp.eq(r1.new, #1)) jump:t 0x81c
+ {
+ r1 = zxth(r2)
+ if (!cmp.eq(r1.new, #1)) jump:t .L2
+ }
+ .org .+2048
+.L2:
+
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