[llvm] r263703 - [mips] Eliminate instances of "potentially uninitialised local variable" warnings, NFC

[Scott Egerton via llvm-commits]

Author: s.egerton
Date: Thu Mar 17 05:37:51 2016
New Revision: 263703

URL: http://llvm.org/viewvc/llvm-project?rev=263703&view=rev
Log:
[mips] Eliminate instances of "potentially uninitialised local variable" warnings, NFC

Summary:
This should eliminate all occurrences of this within LLVMMipsAsmParser.
This patch is in response to http://reviews.llvm.org/D17983. I was unable
to reproduce the warnings on my machine so please advise if this fixes the
warnings.

Reviewers: ariccio, vkalintiris, dsanders

Subscribers: dblaikie, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18087

Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=263703&r1=263702&r2=263703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Mar 17 05:37:51 2016
@@ -2590,8 +2590,7 @@ bool MipsAsmParser::expandBranchImm(MCIn
 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions,
                                   bool isLoad, bool isImmOpnd) {
-  unsigned ImmOffset, HiOffset, LoOffset;
-  const MCExpr *ExprOffset;
+  MCOperand HiOperand, LoOperand;
   unsigned TmpRegNum;
   // 1st operand is either the source or destination register.
   assert(Inst.getOperand(0).isReg() && "expected register operand kind");
@@ -2602,14 +2601,19 @@ void MipsAsmParser::expandMemInst(MCInst
   // 3rd operand is either an immediate or expression.
   if (isImmOpnd) {
     assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
-    ImmOffset = Inst.getOperand(2).getImm();
-    LoOffset = ImmOffset & 0x0000ffff;
-    HiOffset = (ImmOffset & 0xffff0000) >> 16;
+    unsigned ImmOffset = Inst.getOperand(2).getImm();
+    unsigned LoOffset = ImmOffset & 0x0000ffff;
+    unsigned HiOffset = (ImmOffset & 0xffff0000) >> 16;
     // If msb of LoOffset is 1(negative number) we must increment HiOffset.
     if (LoOffset & 0x8000)
       HiOffset++;
-  } else
-    ExprOffset = Inst.getOperand(2).getExpr();
+    LoOperand = MCOperand::createImm(LoOffset);
+    HiOperand = MCOperand::createImm(HiOffset);
+  } else {
+    const MCExpr *ExprOffset = Inst.getOperand(2).getExpr();
+    LoOperand = MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "lo"));
+    HiOperand = MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "hi"));
+  }
   // These are some of the types of expansions we perform here:
   // 1) lw $8, sym        => lui $8, %hi(sym)
   //                         lw $8, %lo(sym)($8)
@@ -2648,20 +2652,13 @@ void MipsAsmParser::expandMemInst(MCInst
       return;
   }
 
-  emitRX(Mips::LUi, TmpRegNum,
-         isImmOpnd ? MCOperand::createImm(HiOffset)
-                   : MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "hi")),
-         IDLoc, Instructions);
+  emitRX(Mips::LUi, TmpRegNum, HiOperand, IDLoc, Instructions);
   // Add temp register to base.
   if (BaseRegNum != Mips::ZERO)
     emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, Instructions);
   // And finally, create original instruction with low part
   // of offset and new base.
-  emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum,
-          isImmOpnd
-              ? MCOperand::createImm(LoOffset)
-              : MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "lo")),
-          IDLoc, Instructions);
+  emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum, LoOperand, IDLoc, Instructions);
 }
 
 bool