[PATCH] D18179: [mips] Correct MIPS16 jal/jalx to have uimm26 offsets and add MC layer range checks. NFC.

[Daniel Sanders via llvm-commits]

dsanders created this revision.
dsanders added a reviewer: vkalintiris.
dsanders added a subscriber: llvm-commits.
Herald added a subscriber: dsanders.

However, this has no effect at this time because the instructions affected
are marked 'isCodeGenOnly=1' and have no alternative for the MC layer.

http://reviews.llvm.org/D18179

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/Mips16InstrInfo.td
  lib/Target/Mips/MipsInstrInfo.td

Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -445,8 +445,10 @@
 //     uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
 //   This is entirely arbitrary. We need an ordering and what we pick is
 //   unimportant since only one is possible for a given mnemonic.
+def ConstantUImm26AsmOperandClass
+    : ConstantUImmAsmOperandClass<26, []>;
 def ConstantUImm20AsmOperandClass
-    : ConstantUImmAsmOperandClass<20, []>;
+    : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
 def UImm16RelaxedAsmOperandClass
     : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
   let Name = "UImm16_Relaxed";
@@ -585,7 +587,6 @@
   let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
-def simm20      : Operand<i32>;
 def simm32      : Operand<i32>;
 
 def simm16_64   : Operand<i64> {
@@ -607,7 +608,7 @@
 }
 
 // Unsigned Operands
-foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20} in
+foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in
   def uimm # I : Operand<i32> {
     let PrintMethod = "printUImm<" # I # ">";
     let ParserMatchClass =
Index: lib/Target/Mips/Mips16InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips16InstrInfo.td
+++ lib/Target/Mips/Mips16InstrInfo.td
@@ -115,16 +115,16 @@
 //
 class FJAL16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins simm20:$imm),
+  FJAL16<_X, (outs), (ins uimm26:$imm),
          !strconcat(asmstr, "\t$imm\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
 }
 
 class FJALB16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins simm20:$imm),
+  FJAL16<_X, (outs), (ins uimm26:$imm),
          !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3794,6 +3794,9 @@
   case Match_UImm20_0:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 20-bit unsigned immediate");
+  case Match_UImm26_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected 26-bit unsigned immediate");
   }
 
   llvm_unreachable("Implement any new match types added!");


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