[PATCH] D18162: AMDGPU: Add SIWholeQuadMode pass

[Nicolai Hähnle via llvm-commits]

nhaehnle created this revision.
nhaehnle added reviewers: arsenm, tstellarAMD, mareko.
nhaehnle added a subscriber: llvm-commits.
Herald added subscribers: arsenm, MatzeB.

Whole quad mode is already enabled for pixel shaders that compute
derivatives, but it must be suspended for instructions that cause a
shader to have side effects (i.e. stores and atomics).

This pass addresses the issue by storing the real (initial) live mask
in a register, masking EXEC before instructions that require exact
execution and (re-)enabling WQM where required.

This pass is run before register coalescing so that we can use
machine SSA for analysis.

The changes in this patch expose a problem with the second machine
scheduling pass: target independent instructions like COPY implicitly
use EXEC when they operate on VGPRs, but this fact is not encoded in
the MIR. This can lead to miscompilation because instructions are
moved past changes to EXEC.

This patch fixes the problem by adding use-implicit operands to
target independent instructions. Some general codegen passes are
relaxed to work with such implicit use operands.

http://reviews.llvm.org/D18162

Files:
  lib/CodeGen/ProcessImplicitDefs.cpp
  lib/CodeGen/TwoAddressInstructionPass.cpp
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/SILowerControlFlow.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SIWholeQuadMode.cpp
  test/CodeGen/AMDGPU/si-scheduler.ll
  test/CodeGen/AMDGPU/wqm.ll

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