[llvm] r263420 - [AMDGPU] Assembler: SOP* instruction fixes
Nikolay Haustov via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 14 04:17:19 PDT 2016
Author: nhaustov
Date: Mon Mar 14 06:17:19 2016
New Revision: 263420
URL: http://llvm.org/viewvc/llvm-project?rev=263420&view=rev
Log:
[AMDGPU] Assembler: SOP* instruction fixes
s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit.
s_rfe_b64 has just one destination operand and no source.
Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that.
Add s_memrealtime test and change comments in smem.s to follow common style.
Change test for s_memtime to use non-zero register to make it really test encoding.
Add tests for s_buffer_load*.
Add tests for SOPC instructions (same for SI and VI)
Differential Revision: http://reviews.llvm.org/D18040
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/test/MC/AMDGPU/smem.s
llvm/trunk/test/MC/AMDGPU/smrd.s
llvm/trunk/test/MC/AMDGPU/sop1.s
llvm/trunk/test/MC/AMDGPU/sopc.s
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=263420&r1=263419&r2=263420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon Mar 14 06:17:19 2016
@@ -901,6 +901,12 @@ multiclass SOP1_32_64 <sop1 op, string o
opName#" $sdst, $src0", pattern
>;
+// 32-bit input, 64-bit output.
+multiclass SOP1_64_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
+ op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0),
+ opName#" $sdst, $src0", pattern
+>;
+
class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
SOP2<outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
@@ -964,19 +970,26 @@ multiclass SOP2_64_32_32 <sop2 op, strin
opName#" $sdst, $src0, $src1", pattern
>;
+class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1,
+ string opName, list<dag> pattern = []> : SOPC <
+ op, (outs), (ins rc0:$src0, rc1:$src1),
+ opName#" $src0, $src1", pattern > {
+ let Defs = [SCC];
+}
class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
- string opName, PatLeaf cond> : SOPC <
- op, (outs), (ins rc:$src0, rc:$src1),
- opName#" $src0, $src1",
+ string opName, PatLeaf cond> : SOPC_Base <
+ op, rc, rc, opName,
[(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > {
- let Defs = [SCC];
}
-class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
+class SOPC_CMP_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
: SOPC_Helper<op, SSrc_32, i32, opName, cond>;
-class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
- : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
+class SOPC_32<bits<7> op, string opName, list<dag> pattern = []>
+ : SOPC_Base<op, SSrc_32, SSrc_32, opName, pattern>;
+
+class SOPC_64_32<bits<7> op, string opName, list<dag> pattern = []>
+ : SOPC_Base<op, SSrc_64, SSrc_32, opName, pattern>;
class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SOPK <outs, ins, "", pattern>,
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=263420&r1=263419&r2=263420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Mon Mar 14 06:17:19 2016
@@ -168,13 +168,13 @@ defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a
>;
defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>;
-defm S_BITSET0_B64 : SOP1_64 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>;
+defm S_BITSET0_B64 : SOP1_64_32 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>;
defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>;
-defm S_BITSET1_B64 : SOP1_64 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>;
+defm S_BITSET1_B64 : SOP1_64_32 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>;
defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>;
defm S_SETPC_B64 : SOP1_1 <sop1<0x20, 0x1d>, "s_setpc_b64", []>;
defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>;
-defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>;
+defm S_RFE_B64 : SOP1_1 <sop1<0x22, 0x1f>, "s_rfe_b64", []>;
let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
@@ -344,23 +344,23 @@ defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c,
// SOPC Instructions
//===----------------------------------------------------------------------===//
-def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>;
-def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32", COND_NE>;
-def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>;
-def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>;
-def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>;
-def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32", COND_SLE>;
-def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>;
-def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32", COND_NE >;
-def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>;
-def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>;
-def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>;
-def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>;
-////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>;
-////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>;
-////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>;
-////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>;
-//def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>;
+def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>;
+def S_CMP_LG_I32 : SOPC_CMP_32 <0x00000001, "s_cmp_lg_i32", COND_NE>;
+def S_CMP_GT_I32 : SOPC_CMP_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>;
+def S_CMP_GE_I32 : SOPC_CMP_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>;
+def S_CMP_LT_I32 : SOPC_CMP_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>;
+def S_CMP_LE_I32 : SOPC_CMP_32 <0x00000005, "s_cmp_le_i32", COND_SLE>;
+def S_CMP_EQ_U32 : SOPC_CMP_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>;
+def S_CMP_LG_U32 : SOPC_CMP_32 <0x00000007, "s_cmp_lg_u32", COND_NE >;
+def S_CMP_GT_U32 : SOPC_CMP_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>;
+def S_CMP_GE_U32 : SOPC_CMP_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>;
+def S_CMP_LT_U32 : SOPC_CMP_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>;
+def S_CMP_LE_U32 : SOPC_CMP_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>;
+def S_BITCMP0_B32 : SOPC_32 <0x0000000c, "s_bitcmp0_b32">;
+def S_BITCMP1_B32 : SOPC_32 <0x0000000d, "s_bitcmp1_b32">;
+def S_BITCMP0_B64 : SOPC_64_32 <0x0000000e, "s_bitcmp0_b64">;
+def S_BITCMP1_B64 : SOPC_64_32 <0x0000000f, "s_bitcmp1_b64">;
+def S_SETVSKIP : SOPC_32 <0x00000010, "s_setvskip">;
//===----------------------------------------------------------------------===//
// SOPK Instructions
Modified: llvm/trunk/test/MC/AMDGPU/smem.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smem.s?rev=263420&r1=263419&r2=263420&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smem.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smem.s Mon Mar 14 06:17:19 2016
@@ -3,9 +3,13 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSI %s
s_dcache_wb
-; VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
-; NOSI: error: instruction not supported on this GPU
+// VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
+// NOSI: error: instruction not supported on this GPU
s_dcache_wb_vol
-; VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
-; NOSI: error: instruction not supported on this GPU
+// VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
+// NOSI: error: instruction not supported on this GPU
+
+s_memrealtime s[4:5]
+// VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
+// NOSI: error: instruction not supported on this GPU
Modified: llvm/trunk/test/MC/AMDGPU/smrd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd.s?rev=263420&r1=263419&r2=263420&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smrd.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smrd.s Mon Mar 14 06:17:19 2016
@@ -80,6 +80,58 @@ s_load_dwordx16 s[88:103], s[2:3], s4
// GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
// NOVI: error: invalid operand for instruction
+s_buffer_load_dword s1, s[4:7], 1
+// GCN: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x01,0x85,0x00,0xc2]
+// VI: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x42,0x00,0x22,0xc0,0x01,0x00,0x00,0x00]
+
+s_buffer_load_dword s1, s[4:7], s4
+// GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2]
+// VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[8:9], s[4:7], 1
+// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x01,0x05,0x44,0xc2]
+// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[8:9], s[4:7], s4
+// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x04,0x04,0x44,0xc2]
+// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x02,0x02,0x24,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[8:11], s[4:7], 1
+// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x01,0x05,0x84,0xc2]
+// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2a,0xc0,0x01,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[8:11], s[4:7], s4
+// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x04,0x04,0x84,0xc2]
+// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[100:103], s[4:7], s4
+// GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]
+// NOVI: error: invalid operand for instruction
+
+s_buffer_load_dwordx8 s[8:15], s[4:7], 1
+// GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x01,0x05,0xc4,0xc2]
+// VI: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2e,0xc0,0x01,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[8:15], s[4:7], s4
+// GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x04,0x04,0xc4,0xc2]
+// VI: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x02,0x02,0x2c,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[96:103], s[4:7], s4
+// GCN: s_buffer_load_dwordx8 s[96:103], s[4:7], s4 ; encoding: [0x04,0x04,0xf0,0xc2]
+// NOVI: error: invalid operand for instruction
+
+s_buffer_load_dwordx16 s[16:31], s[4:7], 1
+// GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x01,0x05,0x08,0xc3]
+// VI: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x02,0x04,0x32,0xc0,0x01,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[16:31], s[4:7], s4
+// GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x04,0x04,0x08,0xc3]
+// VI: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x02,0x04,0x30,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[88:103], s[4:7], s4
+// GCN: s_buffer_load_dwordx16 s[88:103], s[4:7], s4 ; encoding: [0x04,0x04,0x2c,0xc3]
+// NOVI: error: invalid operand for instruction
+
s_dcache_inv
// GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
// VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
@@ -89,6 +141,6 @@ s_dcache_inv_vol
// NOSI: error: instruction not supported on this GPU
// VI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
-s_memtime s[0:1]
-// GCN: s_memtime s[0:1] ; encoding: [0x00,0x00,0x80,0xc7]
-// VI: s_memtime s[0:1] ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00]
+s_memtime s[4:5]
+// GCN: s_memtime s[4:5] ; encoding: [0x00,0x00,0x82,0xc7]
+// VI: s_memtime s[4:5] ; encoding: [0x00,0x01,0x90,0xc0,0x00,0x00,0x00,0x00]
Modified: llvm/trunk/test/MC/AMDGPU/sop1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sop1.s?rev=263420&r1=263419&r2=263420&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sop1.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sop1.s Mon Mar 14 06:17:19 2016
@@ -121,14 +121,14 @@ s_sext_i32_i16 s1, s2
s_bitset0_b32 s1, s2
// CHECK: s_bitset0_b32 s1, s2 ; encoding: [0x02,0x1b,0x81,0xbe]
-s_bitset0_b64 s[2:3], s[4:5]
-// CHECK: s_bitset0_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1c,0x82,0xbe]
+s_bitset0_b64 s[2:3], s4
+// CHECK: s_bitset0_b64 s[2:3], s4 ; encoding: [0x04,0x1c,0x82,0xbe]
s_bitset1_b32 s1, s2
// CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe]
-s_bitset1_b64 s[2:3], s[4:5]
-// CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe]
+s_bitset1_b64 s[2:3], s4
+// CHECK: s_bitset1_b64 s[2:3], s4 ; encoding: [0x04,0x1e,0x82,0xbe]
s_getpc_b64 s[2:3]
// CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe]
@@ -139,8 +139,8 @@ s_setpc_b64 s[4:5]
s_swappc_b64 s[2:3], s[4:5]
// CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe]
-s_rfe_b64 s[2:3], s[4:5]
-// CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe]
+s_rfe_b64 s[4:5]
+// CHECK: s_rfe_b64 s[4:5] ; encoding: [0x04,0x22,0x80,0xbe]
s_and_saveexec_b64 s[2:3], s[4:5]
// CHECK: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x24,0x82,0xbe]
Modified: llvm/trunk/test/MC/AMDGPU/sopc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sopc.s?rev=263420&r1=263419&r2=263420&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sopc.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sopc.s Mon Mar 14 06:17:19 2016
@@ -1,9 +1,58 @@
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s
//===----------------------------------------------------------------------===//
-// Instructions
+// SOPC Instructions
//===----------------------------------------------------------------------===//
s_cmp_eq_i32 s1, s2
// CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
+
+s_cmp_lg_i32 s1, s2
+// CHECK: s_cmp_lg_i32 s1, s2 ; encoding: [0x01,0x02,0x01,0xbf]
+
+s_cmp_gt_i32 s1, s2
+// CHECK: s_cmp_gt_i32 s1, s2 ; encoding: [0x01,0x02,0x02,0xbf]
+
+s_cmp_ge_i32 s1, s2
+// CHECK: s_cmp_ge_i32 s1, s2 ; encoding: [0x01,0x02,0x03,0xbf]
+
+s_cmp_lt_i32 s1, s2
+// CHECK: s_cmp_lt_i32 s1, s2 ; encoding: [0x01,0x02,0x04,0xbf]
+
+s_cmp_le_i32 s1, s2
+// CHECK: s_cmp_le_i32 s1, s2 ; encoding: [0x01,0x02,0x05,0xbf]
+
+s_cmp_eq_u32 s1, s2
+// CHECK: s_cmp_eq_u32 s1, s2 ; encoding: [0x01,0x02,0x06,0xbf]
+
+s_cmp_lg_u32 s1, s2
+// CHECK: s_cmp_lg_u32 s1, s2 ; encoding: [0x01,0x02,0x07,0xbf]
+
+s_cmp_gt_u32 s1, s2
+// CHECK: s_cmp_gt_u32 s1, s2 ; encoding: [0x01,0x02,0x08,0xbf]
+
+s_cmp_ge_u32 s1, s2
+// CHECK: s_cmp_ge_u32 s1, s2 ; encoding: [0x01,0x02,0x09,0xbf]
+
+s_cmp_lt_u32 s1, s2
+// CHECK: s_cmp_lt_u32 s1, s2 ; encoding: [0x01,0x02,0x0a,0xbf]
+
+s_cmp_le_u32 s1, s2
+// CHECK: s_cmp_le_u32 s1, s2 ; encoding: [0x01,0x02,0x0b,0xbf]
+
+s_bitcmp0_b32 s1, s2
+// CHECK: s_bitcmp0_b32 s1, s2 ; encoding: [0x01,0x02,0x0c,0xbf]
+
+s_bitcmp1_b32 s1, s2
+// CHECK: s_bitcmp1_b32 s1, s2 ; encoding: [0x01,0x02,0x0d,0xbf]
+
+s_bitcmp0_b64 s[2:3], s4
+// CHECK: s_bitcmp0_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0e,0xbf]
+
+s_bitcmp1_b64 s[2:3], s4
+// CHECK: s_bitcmp1_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0f,0xbf]
+
+s_setvskip s3, s5
+// CHECK: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]
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