[llvm] r263411 - [AMDGPU] AsmParser: Factor out parseRegister. NFC.

[Valery Pykhtin via llvm-commits]

Author: vpykhtin
Date: Mon Mar 14 02:43:42 2016
New Revision: 263411

URL: http://llvm.org/viewvc/llvm-project?rev=263411&view=rev
Log:
[AMDGPU] AsmParser: Factor out parseRegister. NFC.

Modified:
    llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=263411&r1=263410&r2=263411&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Mar 14 02:43:42 2016
@@ -493,6 +493,7 @@ public:
     return ForcedEncodingSize == 64;
   }
 
+  std::unique_ptr<AMDGPUOperand> parseRegister();
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
@@ -614,22 +615,35 @@ static unsigned getRegForName(StringRef
 }
 
 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
-  const AsmToken Tok = Parser.getTok();
-  StartLoc = Tok.getLoc();
-  EndLoc = Tok.getEndLoc();
+  auto R = parseRegister();
+  if (!R) return true;
+  assert(R->isReg());
+  RegNo = R->getReg();
+  StartLoc = R->getStartLoc();
+  EndLoc = R->getEndLoc();
+  return false;
+}
+
+std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
+  const AsmToken &Tok = Parser.getTok();
+  SMLoc StartLoc = Tok.getLoc();
+  SMLoc EndLoc = Tok.getEndLoc();
   const MCRegisterInfo *TRI = getContext().getRegisterInfo();
 
   StringRef RegName = Tok.getString();
-  RegNo = getRegForName(RegName);
+  unsigned RegNo = getRegForName(RegName);
 
   if (RegNo) {
     Parser.Lex();
-    return !subtargetHasRegister(*TRI, RegNo);
+    if (!subtargetHasRegister(*TRI, RegNo))
+      return nullptr;
+    return AMDGPUOperand::CreateReg(RegNo, StartLoc, EndLoc,
+                                    TRI, &getSTI(), false);
   }
 
   // Match vgprs and sgprs
   if (RegName[0] != 's' && RegName[0] != 'v')
-    return true;
+    return nullptr;
 
   bool IsVgpr = RegName[0] == 'v';
   unsigned RegWidth;
@@ -638,7 +652,7 @@ bool AMDGPUAsmParser::ParseRegister(unsi
     // We have a 32-bit register
     RegWidth = 1;
     if (RegName.substr(1).getAsInteger(10, RegIndexInClass))
-      return true;
+      return nullptr;
     Parser.Lex();
   } else {
     // We have a register greater than 32-bits.
@@ -646,21 +660,21 @@ bool AMDGPUAsmParser::ParseRegister(unsi
     int64_t RegLo, RegHi;
     Parser.Lex();
     if (getLexer().isNot(AsmToken::LBrac))
-      return true;
+      return nullptr;
 
     Parser.Lex();
     if (getParser().parseAbsoluteExpression(RegLo))
-      return true;
+      return nullptr;
 
     if (getLexer().isNot(AsmToken::Colon))
-      return true;
+      return nullptr;
 
     Parser.Lex();
     if (getParser().parseAbsoluteExpression(RegHi))
-      return true;
+      return nullptr;
 
     if (getLexer().isNot(AsmToken::RBrac))
-      return true;
+      return nullptr;
 
     Parser.Lex();
     RegWidth = (RegHi - RegLo) + 1;
@@ -671,7 +685,7 @@ bool AMDGPUAsmParser::ParseRegister(unsi
       // SGPR registers are aligned.  Max alignment is 4 dwords.
       unsigned Size = std::min(RegWidth, 4u);
       if (RegLo % Size != 0)
-        return true;
+        return nullptr;
 
       RegIndexInClass = RegLo / Size;
     }
@@ -679,14 +693,18 @@ bool AMDGPUAsmParser::ParseRegister(unsi
 
   int RCID = getRegClass(IsVgpr, RegWidth);
   if (RCID == -1)
-    return true;
+    return nullptr;
 
   const MCRegisterClass RC = TRI->getRegClass(RCID);
   if (RegIndexInClass >= RC.getNumRegs())
-    return true;
+    return nullptr;
 
   RegNo = RC.getRegister(RegIndexInClass);
-  return !subtargetHasRegister(*TRI, RegNo);
+  if (!subtargetHasRegister(*TRI, RegNo))
+    return nullptr;
+
+  return AMDGPUOperand::CreateReg(RegNo, StartLoc, EndLoc,
+                                  TRI, &getSTI(), false);
 }
 
 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
@@ -1085,9 +1103,7 @@ AMDGPUAsmParser::parseOperand(OperandVec
       return MatchOperand_Success;
     }
     case AsmToken::Identifier: {
-      SMLoc S, E;
-      unsigned RegNo;
-      if (!ParseRegister(RegNo, S, E)) {
+      if (auto R = parseRegister()) {
         unsigned Modifiers = 0;
 
         if (Negate)
@@ -1106,9 +1122,8 @@ AMDGPUAsmParser::parseOperand(OperandVec
           Parser.Lex();
           Modifiers |= 0x2;
         }
-        auto R = AMDGPUOperand::CreateReg(RegNo, S, E,
-                                          getContext().getRegisterInfo(),
-                                          &getSTI(), isForcedVOP3());
+        assert(R->isReg());
+        R->Reg.IsForcedVOP3 = isForcedVOP3();
         if (Modifiers) {
           R->setModifiers(Modifiers);
         }
@@ -1116,8 +1131,9 @@ AMDGPUAsmParser::parseOperand(OperandVec
       } else {
         ResTy = parseVOP3OptionalOps(Operands);
         if (ResTy == MatchOperand_NoMatch) {
-          Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),
-                                                        S));
+          const auto &Tok = Parser.getTok();
+          Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(),
+                                                        Tok.getLoc()));
           Parser.Lex();
         }
       }