[PATCH] D14840: [X86] Detect SAD patterns and emit psadbw instructions on X86.

[Cong Hou via llvm-commits]

congh added a comment.

In http://reviews.llvm.org/D14840#373057, @RKSimon wrote:

> What would be necessary to enable PSADBW to match for SSE2 in the 32i8/64i8 cases (and AVX2/AVX512F in the 64i8 case)?


Then we need to consider this case in detectSADPattern: currently we don't handle too long registers. This is ok in aspect of auto-vectorization as we won't get too long vectors, so I am wondering if it is worth the effort to handle those cases. If we want to do it, we need to tell X86 isel how to split X86ISD::PSADBW. What do you think?


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13643
@@ -13642,3 +13642,3 @@
   SDValue N0 = N->getOperand(0);
   SDValue N2 = N->getOperand(2);
 
----------------
RKSimon wrote:
> We're referencing N->getOperand(1) enough now that we can bring this out as N1.
Done.

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13650
@@ +13649,3 @@
+    if (N0.getValueType() != N->getOperand(1).getValueType())
+      return SDValue();
+
----------------
RKSimon wrote:
> Add this condition to the outer if()
OK.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:29046
@@ +29045,3 @@
+  // The second operand of SelectOp Op1 is the negation of the first operand
+  // Op0, which is implementes as 0 - Op0.
+  if (!(Op1.getOpcode() == ISD::SUB &&
----------------
RKSimon wrote:
> implemented
Done.


http://reviews.llvm.org/D14840