[llvm] r263268 - Update test case to appease bots after 263255.

[Chad Rosier via llvm-commits]

Hi Matt/Tom,
The change in r263255 fixed an issue when comparing signed and unsigned
offsets in the load clustering mutation in the MI scheduler.  Fixing the
sorting caused the order of SU(7) and SU(8) to change, which I believe now
is the correct ordering.

Previously, the ordering was:
SU(7):   %vreg11<def> = DS_READ_B32 %vreg28, 256, 0, %M0<imp-use>,
%EXEC<imp-use>;
SU(8):   %vreg13<def> = DS_READ_B32 %vreg28, -256, 0, %M0<imp-use,kill>,
%EXEC<imp-use>;

And now they're
SU(8):   %vreg13<def> = DS_READ_B32 %vreg28, -256, 0, %M0<imp-use,kill>,
%EXEC<imp-use>;
SU(7):   %vreg11<def> = DS_READ_B32 %vreg28, 256, 0, %M0<imp-use>,
%EXEC<imp-use>;

since the sort is in ascending order.  Please let me know if I've missed
anything or if you are concerned with the change to the test case.

 Chad

> Author: mcrosier
> Date: Fri Mar 11 11:33:36 2016
> New Revision: 263268
>
> URL: http://llvm.org/viewvc/llvm-project?rev=263268&view=rev
> Log:
> Update test case to appease bots after 263255.
>
> I'll follow up with Matt to confirm this is the correct fix.
>
> Modified:
>     llvm/trunk/test/CodeGen/AMDGPU/ds_read2st64.ll
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/ds_read2st64.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ds_read2st64.ll?rev=263268&r1=263267&r2=263268&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/ds_read2st64.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/ds_read2st64.ll Fri Mar 11 11:33:36
> 2016
> @@ -44,9 +44,9 @@ define void @simple_read2st64_f32_1_2(fl
>  }
>
>  ; SI-LABEL: @simple_read2st64_f32_max_offset
> -; SI: ds_read2st64_b32
> v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1
> offset1:255
> +; SI: ds_read2st64_b32
> v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}}
> offset0:255 offset1:1
>  ; SI: s_waitcnt lgkmcnt(0)
> -; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
> +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]]
>  ; SI: buffer_store_dword [[RESULT]]
>  ; SI: s_endpgm
>  define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out,
> float addrspace(3)* %lds) #0 {
> @@ -176,9 +176,9 @@ define void @misaligned_read2st64_f64(do
>
>  ; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff
>  ; SI-LABEL: @simple_read2st64_f64_max_offset
> -; SI: ds_read2st64_b64
> v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4
> offset1:127
> +; SI: ds_read2st64_b64
> v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}}
> offset0:127 offset1:4
>  ; SI: s_waitcnt lgkmcnt(0)
> -; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]],
> v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
> +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]],
> v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}, v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}
>  ; SI: buffer_store_dwordx2 [[RESULT]]
>  ; SI: s_endpgm
>  define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out,
> double addrspace(3)* %lds) #0 {
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>