[PATCH] D17966: [AMDGPU] Fix VOPC instruction operand namings

Valery Pykhtin via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 11 06:58:28 PST 2016


This revision was automatically updated to reflect the committed changes.
Closed by commit rL263242: [AMDGPU] Fix VOPC instruction operand namings (authored by vpykhtin).

Changed prior to commit:
  http://reviews.llvm.org/D17966?vs=50060&id=50426#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D17966

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
  llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt

Index: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
@@ -445,10 +445,10 @@
 
 class VOPCe <bits<8> op> : Enc32 {
   bits<9> src0;
-  bits<8> vsrc1;
+  bits<8> src1;
 
   let Inst{8-0} = src0;
-  let Inst{16-9} = vsrc1;
+  let Inst{16-9} = src1;
   let Inst{24-17} = op;
   let Inst{31-25} = 0x3e;
 }
Index: llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+# VI:   v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
+0x02 0x08 0x82 0x7c
+
+# VI:   v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
+0x80 0x08 0x82 0x7c
+
+# VI:   v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
+0x02 0x09 0x82 0x7c
+
+# VI:   v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
+0x02 0x09 0x80 0x7c
+
+# VI:   v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
+0x02 0x09 0x82 0x7c
+
+# VI:   v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
+0x02 0x09 0xc0 0x7c
+
+# VI:   v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
+0x02 0x09 0x80 0x7d
+
+# VI:   v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
+0x02 0x09 0xc0 0x7d


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