[llvm] r263242 - [AMDGPU] Fix VOPC instruction operand namings

[Valery Pykhtin via llvm-commits]

Author: vpykhtin
Date: Fri Mar 11 08:53:28 2016
New Revision: 263242

URL: http://llvm.org/viewvc/llvm-project?rev=263242&view=rev
Log:
[AMDGPU] Fix VOPC instruction operand namings

Differential Revision: http://reviews.llvm.org/D17966

Added:
    llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=263242&r1=263241&r2=263242&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Fri Mar 11 08:53:28 2016
@@ -445,10 +445,10 @@ class VOP3be <bits<9> op> : Enc64 {
 
 class VOPCe <bits<8> op> : Enc32 {
   bits<9> src0;
-  bits<8> vsrc1;
+  bits<8> src1;
 
   let Inst{8-0} = src0;
-  let Inst{16-9} = vsrc1;
+  let Inst{16-9} = src1;
   let Inst{24-17} = op;
   let Inst{31-25} = 0x3e;
 }

Added: llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt?rev=263242&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt Fri Mar 11 08:53:28 2016
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+# VI:   v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
+0x02 0x08 0x82 0x7c
+
+# VI:   v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
+0x80 0x08 0x82 0x7c
+
+# VI:   v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
+0x02 0x09 0x82 0x7c
+
+# VI:   v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
+0x02 0x09 0x80 0x7c
+
+# VI:   v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
+0x02 0x09 0x82 0x7c
+
+# VI:   v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
+0x02 0x09 0xc0 0x7c
+
+# VI:   v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
+0x02 0x09 0x80 0x7d
+
+# VI:   v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
+0x02 0x09 0xc0 0x7d