[PATCH] D18032: Power 9 Atomic instructions, load monitored and move XER to CR

[Chuang-Yu Cheng via llvm-commits]

cycheng added inline comments.

================
Comment at: lib/Target/PowerPC/PPCInstr64Bit.td:248
@@ +247,3 @@
+
+let hasExtraSrcRegAllocReq = 1 in
+def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
----------------
Depending on FC value, input might be $(rD+1), $(rD+2)
I believe that's why we need "hasExtraSrcRegAllocReq".

I am curious about the effect of "hasExtraSrcRegAllocReq", looks like it disallows register changing in AggressiveAntiDepBreaker::ScanInstruction, because it is dangerous to do that for this instruction.

================
Comment at: lib/Target/PowerPC/PPCInstr64Bit.td:249
@@ +248,3 @@
+let hasExtraSrcRegAllocReq = 1 in
+def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
+                         "ldat $rD, $rA, $FC", IIC_LdStLoad>,
----------------
Do we need to check $FC value? Or it's user's responsibility?

Even though it looks like user's responsibility:
> an Invalid function code will cause the system data storage error handler to be invoked.

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Comment at: lib/Target/PowerPC/PPCInstr64Bit.td:920
@@ +919,3 @@
+def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
+                   "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
+           Requires<[IsISA3_0]>;
----------------
I don't know when we need to add "isPPC64", Does LDAT and STDAT also require this attribute?


Repository:
  rL LLVM

http://reviews.llvm.org/D18032