[llvm] r263169 - AArch64: only try to use scaled fcvt ops on legal vector types.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Thu Mar 10 17:02:21 2016
New Revision: 263169

URL: http://llvm.org/viewvc/llvm-project?rev=263169&view=rev
Log:
AArch64: only try to use scaled fcvt ops on legal vector types.

Before we ended up calling getSimpleVectorType on a <3 x float>, which
asserted.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/fcvt_combine.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=263169&r1=263168&r2=263169&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Mar 10 17:02:21 2016
@@ -7687,7 +7687,8 @@ static SDValue performFpToIntCombine(SDN
     return SDValue();
 
   SDValue Op = N->getOperand(0);
-  if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
+  if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
+      Op.getOpcode() != ISD::FMUL)
     return SDValue();
 
   SDValue ConstVec = Op->getOperand(1);

Modified: llvm/trunk/test/CodeGen/AArch64/fcvt_combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fcvt_combine.ll?rev=263169&r1=263168&r2=263169&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fcvt_combine.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fcvt_combine.ll Thu Mar 10 17:02:21 2016
@@ -152,3 +152,11 @@ define <2 x i32> @test14(<2 x float> %f)
   %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
   ret <2 x i32> %vcvt.i
 }
+
+; CHECK-LABEL: test_illegal_fp_to_int:
+; CHECK: fcvtzs.4s v0, v0, #2
+define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
+  %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
+  %val = fptosi <3 x float> %scale to <3 x i32>
+  ret <3 x i32> %val
+}