[PATCH] D18030: [ppc64] Create instruction reorder chances in prologue and epilogue for post-RA-scheduler

[Chuang-Yu Cheng via llvm-commits]

cycheng created this revision.
cycheng added reviewers: hfinkel, tjablin, nemanjai, kbarton, amehsan.
cycheng added a subscriber: llvm-commits.
Herald added a subscriber: MatzeB.

This patch changes SPUpdate (stack pointer update) instruction position in prologue and epilogue, in order to  create more reorder chances for scheduler. Concept as below example:

```
  Current          This Patch

prologue:
  mflr 0           stdu 1, -240(1)
  mfcr 12          ..
  std 0, 16(1)     (scheduler gets more reorder chances)
  stw 12, 8(1)
  stdu 1, -240(1)

epilogue:
  addi 1, 1, 240   (scheduler gets more reorder chances)
  ld 0, 16(1)
  lwz 12, 8(1)
  mtocrf 32, 12
  mtlr 0           addi 1, 1, 240
  blr              blr
```
It moves SPUpdate to the beginning of prologue, and to the end (before return) of epilogue, so it can create more chances for scheduler to reorder mflr/mfcr/lr store/cr store, as well as mtlr/mtocrf/lr load/cr load.

Original issue: https://llvm.org/bugs/show_bug.cgi?id=25685

Ths patch passed bootstrap testing, SPEC2006 testing. We also benchmarked by SPEC2006, and it show good result:

403.gcc: +3%
429.mcf: +10%
462.libquantum: 7%
464.h264ref: 1%
433.milc: 3%
450.solpex: 8%


http://reviews.llvm.org/D18030

Files:
  lib/Target/PowerPC/PPCFrameLowering.cpp
  lib/Target/PowerPC/PPCInstr64Bit.td
  lib/Target/PowerPC/PPCScheduleP8.td
  test/CodeGen/PowerPC/crsave.ll
  test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
  test/CodeGen/PowerPC/ppc64-calls.ll
  test/CodeGen/PowerPC/ppc64-nest.ll
  test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
  test/CodeGen/PowerPC/retaddr2.ll
  test/CodeGen/PowerPC/sjlj.ll

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