[llvm] r263035 - [PPC] backend changes to generate xvabs[s, d]p and xvnabs[s, d]p instructions

[Kit Barton via llvm-commits]

Author: kbarton
Date: Wed Mar  9 11:48:01 2016
New Revision: 263035

URL: http://llvm.org/viewvc/llvm-project?rev=263035&view=rev
Log:
[PPC] backend changes to generate xvabs[s,d]p and xvnabs[s,d]p instructions

This has to be committed before the FE changes

Phabricator: http://reviews.llvm.org/D17837

Added:
    llvm/trunk/test/CodeGen/PowerPC/vec_abs.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=263035&r1=263034&r2=263035&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Mar  9 11:48:01 2016
@@ -649,6 +649,8 @@ PPCTargetLowering::PPCTargetLowering(con
 
       setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
       setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
+      setOperationAction(ISD::FABS, MVT::v4f32, Legal);
+      setOperationAction(ISD::FABS, MVT::v2f64, Legal);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
     }

Added: llvm/trunk/test/CodeGen/PowerPC/vec_abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_abs.ll?rev=263035&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_abs.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_abs.ll Wed Mar  9 11:48:01 2016
@@ -0,0 +1,80 @@
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=+vsx |  FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=-vsx |  FileCheck %s \
+; RUN:          -check-prefix=CHECK-NOVSX
+
+define <4 x float> @test_float(<4 x float> %aa) #0 {
+
+; CHECK-LABEL: test_float
+; CHECK-NOVSX-LABEL: test_float
+; CHECK-NOVSX-LABEL: test_float
+
+  entry:
+    %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %aa) #2
+    ret <4 x float> %0
+}
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
+
+; CHECK: xvabssp
+; CHECK: blr
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: blr
+
+define <4 x float> @test2_float(<4 x float> %aa) #0 {
+
+; CHECK-LABEL: test2_float
+; CHECK-NOVSX-LABEL: test2_float
+
+  entry:
+    %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %aa) #2
+    %sub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00,
+                             float -0.000000e+00, float -0.000000e+00>, %0
+    ret <4 x float> %sub
+}
+
+; CHECK: xvnabssp
+; CHECK: blr
+; CHECK-NOVSX: vspltisb
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: vsubfp
+; CHECK-NOVSX: blr
+
+define <2 x double> @test_double(<2 x double> %aa) #0 {
+
+; CHECK-LABEL: test_double
+; CHECK-NOVSX-LABEL: test_double
+
+  entry:
+    %0 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %aa) #2
+    ret <2 x double> %0
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #1
+
+; CHECK: xvabsdp
+; CHECK: blr
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: blr
+
+define <2 x double> @foo(<2 x double> %aa) #0 {
+  entry:
+    %0 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %aa) #2
+    %sub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %0
+    ret <2 x double> %sub
+}
+
+; CHECK: xvnabsdp
+; CHECK: blr
+; CHECK-NOVSX: fnabs
+; CHECK-NOVSX: fnabs
+; CHECK-NOVSX: blr