[llvm] r263024 - [AArch64] Minor cleanup/remove redundant code. NFC.
Chad Rosier via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 9 08:46:49 PST 2016
Author: mcrosier
Date: Wed Mar 9 10:46:48 2016
New Revision: 263024
URL: http://llvm.org/viewvc/llvm-project?rev=263024&view=rev
Log:
[AArch64] Minor cleanup/remove redundant code. NFC.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=263024&r1=263023&r2=263024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Wed Mar 9 10:46:48 2016
@@ -618,8 +618,8 @@ AArch64InstrInfo::areMemAccessesTriviall
AliasAnalysis *AA) const {
const TargetRegisterInfo *TRI = &getRegisterInfo();
unsigned BaseRegA = 0, BaseRegB = 0;
- int OffsetA = 0, OffsetB = 0;
- int WidthA = 0, WidthB = 0;
+ int64_t OffsetA = 0, OffsetB = 0;
+ unsigned WidthA = 0, WidthB = 0;
assert(MIa && MIa->mayLoadOrStore() && "MIa must be a load or store.");
assert(MIb && MIb->mayLoadOrStore() && "MIb must be a load or store.");
@@ -1319,6 +1319,7 @@ bool AArch64InstrInfo::getMemOpBaseRegIm
switch (LdSt->getOpcode()) {
default:
return false;
+ // Scaled instructions.
case AArch64::STRSui:
case AArch64::STRDui:
case AArch64::STRQui:
@@ -1329,18 +1330,13 @@ bool AArch64InstrInfo::getMemOpBaseRegIm
case AArch64::LDRQui:
case AArch64::LDRXui:
case AArch64::LDRWui:
- if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
- return false;
- BaseReg = LdSt->getOperand(1).getReg();
- MachineFunction &MF = *LdSt->getParent()->getParent();
- unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();
- Offset = LdSt->getOperand(2).getImm() * Width;
- return true;
+ unsigned Width;
+ return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI);
};
}
bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(
- MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width,
+ MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
const TargetRegisterInfo *TRI) const {
// Handle only loads/stores with base register followed by immediate offset.
if (LdSt->getNumOperands() != 3)
@@ -1350,7 +1346,7 @@ bool AArch64InstrInfo::getMemOpBaseRegIm
// Offset is calculated as the immediate operand multiplied by the scaling factor.
// Unscaled instructions have scaling factor set to 1.
- int Scale = 0;
+ unsigned Scale = 0;
switch (LdSt->getOpcode()) {
default:
return false;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=263024&r1=263023&r2=263024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Wed Mar 9 10:46:48 2016
@@ -95,7 +95,7 @@ public:
const TargetRegisterInfo *TRI) const override;
bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
- int &Offset, int &Width,
+ int64_t &Offset, unsigned &Width,
const TargetRegisterInfo *TRI) const;
bool enableClusterLoads() const override { return true; }
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