[PATCH] D17994: AVX-512: Fixed a bug in shuffle for v64i8 type

[Elena Demikhovsky via llvm-commits]

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A bug is in SCALAR_TO_VECTOR lowering.
The failure:
LLVM ERROR: Cannot select: t18: v32i16 = scalar_to_vector Constant:i16<1>
  t14: i16 = Constant<1>

Repository:
  rL LLVM

http://reviews.llvm.org/D17994

Files:
  ../lib/Target/X86/X86ISelLowering.cpp
  ../test/CodeGen/X86/vector-shuffle-512-v64.ll

Index: ../test/CodeGen/X86/vector-shuffle-512-v64.ll
===================================================================
--- ../test/CodeGen/X86/vector-shuffle-512-v64.ll
+++ ../test/CodeGen/X86/vector-shuffle-512-v64.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f -mattr=+avx512bw -mattr=+avx512vl -mattr=+avx512dq | FileCheck %s
+
+target triple = "x86_64-unknown-unknown"
+
+define <64 x i8> @shuffle_v64i8_02_03_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u(<64 x i8> %a)  {
+; CHECK-LABEL: shuffle_v64i8_02_03_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u_u:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    vmovd %eax, %xmm1
+; CHECK-NEXT:    vpermw %zmm0, %zmm1, %zmm0
+; CHECK-NEXT:    retq
+  %b = shufflevector <64 x i8> %a, <64 x i8> undef, <64 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <64 x i8> %b
+}
Index: ../lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- ../lib/Target/X86/X86ISelLowering.cpp
+++ ../lib/Target/X86/X86ISelLowering.cpp
@@ -1651,6 +1651,8 @@
     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v64i8, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
+    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v32i16, Custom);
+    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v64i8, Custom);
     setOperationAction(ISD::SELECT,             MVT::v32i1, Custom);
     setOperationAction(ISD::SELECT,             MVT::v64i1, Custom);
     setOperationAction(ISD::SIGN_EXTEND,        MVT::v32i8, Custom);


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