[PATCH] D17885: [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance

[Chuang-Yu Cheng via llvm-commits]

cycheng marked 2 inline comments as done.

================
Comment at: lib/Target/PowerPC/PPCInstrInfo.td:4145
@@ +4144,3 @@
+                          "addpcis $rD, $IMM", IIC_IntSimple, []>;
+def SUBPCIS : PPCAsmPseudo<"subpcis $rD, $IMM", (ins gprc:$rD, s16imm:$IMM)>;
+
----------------
nemanjai wrote:
> I'm just curious why the decision to provide one extended mnemonic (`subpcis`) but not the other (`lnia`).
I missed it, thanks : P
That means gcc also forgot to implement it @@

================
Comment at: lib/Target/PowerPC/PPCInstrInfo.td:4155
@@ +4154,3 @@
+                             "dtstsfi $BF, $UIM, $FRB", IIC_FPGeneral, []>;
+def DTSTSFIQ : X_BF3_IM6_RS5<63,  675,
+                             (outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB),
----------------
nemanjai wrote:
> How does this encode the floating register pair? Actually, I just noticed that you have a comment regarding this in the README. SystemZ has already done something like this (the FP128 and GR128 register classes). Perhaps we should do something along those lines.
> 
> This will also help us implement the instructions that are missing from previous versions of the ISA (lq, lfdp, lqarx, et. al.).
Thanks your guide, I found useful information from SystemZ and Sparc.

I did something like this, passed building, but not as my expectation:

```
// Paired F8RC
def subreg_l64   : SubRegIndex<64, 0>;
def subreg_h64   : SubRegIndex<64, 64>;

class DQPR<FPR even, FPR odd, string n> : PPCReg<n> {
  let HWEncoding = even.HWEncoding;
  let SubRegs = [even, odd];
  let SubRegIndices = [subreg_l64, subreg_h64];
}

foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] in {
  def DQ#!srl(Index, 1) :
    DQPR<!cast<FPR>("F"#Index), !cast<FPR>("F"#!add(Index, 1)), "f"#Index>;
}

def F8PRC : RegisterClass<"PPC", [f128], 128, (add (sequence "DQ%u",  0, 6),
                                                   (sequence "DQ%u", 15, 7))>;
def PPCRegQFRCAsmOperand : AsmOperandClass {
  let Name = "RegF8PRC"; let PredicateMethod = "isRegNumber";
}
def f8prc : RegisterOperand<F8PRC> {
  let ParserMatchClass = PPCRegQFRCAsmOperand;
}
```



http://reviews.llvm.org/D17885