[PATCH] D17932: [X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware

[Simon Pilgrim via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: congh, qcolombet, spatel.
RKSimon added a subscriber: llvm-commits.
RKSimon set the repository for this revision to rL LLVM.

Improve vector extension of vectors on hardware without dedicated VSEXT/VZEXT instructions.

We already convert these to SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve this by using the legalizer instead of prematurely splitting into legal vectors in the combine as this only properly helps for lowering to VSEXT/VZEXT.

Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718).

Repository:
  rL LLVM

http://reviews.llvm.org/D17932

Files:
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-zext.ll

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