[PATCH] D17913: AVX512BW: Support llvm intrinsic masked vector load/store for i8/i16 element types on SKX

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:20834
@@ -20820,2 +20833,3 @@
   MVT VT = DataToStore.getSimpleValueType();
+  MVT ScalarVT = VT.getVectorElementType();
   SDValue Mask = N->getMask();
----------------
You use ScalarVT in assert. Buildbot will fail.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:20837
@@ -20822,16 +20836,3 @@
   SDLoc dl(Op);
-
-  if (Subtarget.hasAVX512() && !Subtarget.hasVLX() &&
-      !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
-    // This operation is legal for targets with VLX, but without
-    // VLX the vector should be widened to 512 bit
-    unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
-    MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
-    MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
-    DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
-    Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
-    return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
-                              Mask, N->getMemoryVT(), N->getMemOperand(),
-                              N->isTruncatingStore());
-  }
-  return Op;
+//igorb
+  assert(Subtarget.hasAVX512() && !Subtarget.hasVLX() && !VT.is512BitVector() &&
----------------
remove this comment


Repository:
  rL LLVM

http://reviews.llvm.org/D17913