[PATCH] D17878: Fix DivRem DAGCombine not to assume div/rem type is simple

[Michael Kuperstein via llvm-commits]

mkuper created this revision.
mkuper added reviewers: tyomitch, rengolin.
mkuper added a subscriber: llvm-commits.

The divrem combine assumes the type of the div/rem is simple, which isn't necessarily true.
I'm guessing that it worked fine until r250825, since it probably only saw legal types, but now breaks when it runs as a pre-type-legalization combine.

This fixes PR26835.

http://reviews.llvm.org/D17878

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/pr26835.ll

Index: test/CodeGen/X86/pr26835.ll
===================================================================
--- test/CodeGen/X86/pr26835.ll
+++ test/CodeGen/X86/pr26835.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux"
+
+; CHECK-LABEL: foo
+; CHECK: div
+define i24 @foo(i24 %a, i24 %b) {
+  %r = urem i24 %a, %b
+  ret i24 %r
+}
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2136,7 +2136,10 @@
 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
                                      const TargetLowering &TLI) {
   RTLIB::Libcall LC;
-  switch (Node->getSimpleValueType(0).SimpleTy) {
+  EVT NodeType = Node->getValueType(0);
+  if (!NodeType.isSimple())
+    return false;
+  switch (NodeType.getSimpleVT().SimpleTy) {
   default: return false; // No libcall for vector types.
   case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
   case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;


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