[llvm] r262774 - Add DAG mutation interface to the post-RA scheduler
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 5 07:45:23 PST 2016
Author: kparzysz
Date: Sat Mar 5 09:45:23 2016
New Revision: 262774
URL: http://llvm.org/viewvc/llvm-project?rev=262774&view=rev
Log:
Add DAG mutation interface to the post-RA scheduler
Differential Revision: http://reviews.llvm.org/D17868
Added:
llvm/trunk/include/llvm/CodeGen/ScheduleDAGMutation.h
Modified:
llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=262774&r1=262773&r2=262774&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineScheduler.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineScheduler.h Sat Mar 5 09:45:23 2016
@@ -81,6 +81,7 @@
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
+#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include <memory>
namespace llvm {
@@ -220,15 +221,6 @@ public:
virtual void releaseBottomNode(SUnit *SU) = 0;
};
-/// Mutate the DAG as a postpass after normal DAG building.
-class ScheduleDAGMutation {
- virtual void anchor();
-public:
- virtual ~ScheduleDAGMutation() {}
-
- virtual void apply(ScheduleDAGMI *DAG) = 0;
-};
-
/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply
/// schedules machine instructions according to the given MachineSchedStrategy
/// without much extra book-keeping. This is the common functionality between
Added: llvm/trunk/include/llvm/CodeGen/ScheduleDAGMutation.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGMutation.h?rev=262774&view=auto
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAGMutation.h (added)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAGMutation.h Sat Mar 5 09:45:23 2016
@@ -0,0 +1,31 @@
+//==- ScheduleDAGMutation.h - MachineInstr Scheduling ------------*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the ScheduleDAGMutation class, which represents
+// a target-specific mutation of the dependency graph for scheduling.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
+#define LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
+
+namespace llvm {
+ class ScheduleDAGInstrs;
+
+ /// Mutate the DAG as a postpass after normal DAG building.
+ class ScheduleDAGMutation {
+ virtual void anchor();
+ public:
+ virtual ~ScheduleDAGMutation() {}
+
+ virtual void apply(ScheduleDAGInstrs *DAG) = 0;
+ };
+}
+
+#endif
Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=262774&r1=262773&r2=262774&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Sat Mar 5 09:45:23 2016
@@ -16,8 +16,10 @@
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
+#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h"
+#include <vector>
namespace llvm {
@@ -165,6 +167,12 @@ public:
return CriticalPathRCs.clear();
}
+ // \brief Provide an ordered list of schedule DAG mutations for the post-RA
+ // scheduler.
+ virtual void getPostRAMutations(
+ std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
+ }
+
// For use with PostRAScheduling: get the minimum optimization level needed
// to enable post-RA scheduling.
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=262774&r1=262773&r2=262774&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Sat Mar 5 09:45:23 2016
@@ -1377,7 +1377,7 @@ public:
const TargetRegisterInfo *tri)
: TII(tii), TRI(tri) {}
- void apply(ScheduleDAGMI *DAG) override;
+ void apply(ScheduleDAGInstrs *DAGInstrs) override;
protected:
void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
};
@@ -1429,7 +1429,9 @@ void LoadClusterMutation::clusterNeighbo
}
/// \brief Callback from DAG postProcessing to create cluster edges for loads.
-void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
+void LoadClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
+ ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
+
// Map DAG NodeNum to store chain ID.
DenseMap<unsigned, unsigned> StoreChainIDs;
// Map each store chain to a set of dependent loads.
@@ -1474,7 +1476,7 @@ public:
MacroFusion(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI)
: TII(TII), TRI(TRI) {}
- void apply(ScheduleDAGMI *DAG) override;
+ void apply(ScheduleDAGInstrs *DAGInstrs) override;
};
} // anonymous
@@ -1494,7 +1496,9 @@ static bool HasDataDep(const TargetRegis
/// \brief Callback from DAG postProcessing to create cluster edges to encourage
/// fused operations.
-void MacroFusion::apply(ScheduleDAGMI *DAG) {
+void MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
+ ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
+
// For now, assume targets can only fuse with the branch.
SUnit &ExitSU = DAG->ExitSU;
MachineInstr *Branch = ExitSU.getInstr();
@@ -1545,7 +1549,7 @@ class CopyConstrain : public ScheduleDAG
public:
CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
- void apply(ScheduleDAGMI *DAG) override;
+ void apply(ScheduleDAGInstrs *DAGInstrs) override;
protected:
void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
@@ -1698,7 +1702,8 @@ void CopyConstrain::constrainLocalCopy(S
/// \brief Callback from DAG postProcessing to create weak edges to encourage
/// copy elimination.
-void CopyConstrain::apply(ScheduleDAGMI *DAG) {
+void CopyConstrain::apply(ScheduleDAGInstrs *DAGInstrs) {
+ ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=262774&r1=262773&r2=262774&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Sat Mar 5 09:45:23 2016
@@ -128,6 +128,9 @@ namespace {
/// The schedule. Null SUnit*'s represent noop instructions.
std::vector<SUnit*> Sequence;
+ /// Ordered list of DAG postprocessing steps.
+ std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
+
/// The index in BB of RegionEnd.
///
/// This is the instruction number from the top of the current block, not
@@ -176,6 +179,9 @@ namespace {
void finishBlock() override;
private:
+ /// Apply each ScheduleDAGMutation step in order.
+ void postprocessDAG();
+
void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
void ReleaseSuccessors(SUnit *SU);
void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
@@ -203,6 +209,7 @@ SchedulePostRATDList::SchedulePostRATDLi
HazardRec =
MF.getSubtarget().getInstrInfo()->CreateTargetPostRAHazardRecognizer(
InstrItins, this);
+ MF.getSubtarget().getPostRAMutations(Mutations);
assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE ||
MRI.tracksLiveness()) &&
@@ -429,6 +436,12 @@ void SchedulePostRATDList::finishBlock()
ScheduleDAGInstrs::finishBlock();
}
+/// Apply each ScheduleDAGMutation step in order.
+void SchedulePostRATDList::postprocessDAG() {
+ for (auto &M : Mutations)
+ M->apply(this);
+}
+
//===----------------------------------------------------------------------===//
// Top-Down Scheduling
//===----------------------------------------------------------------------===//
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