[llvm] r262768 - RegisterCoalescer: Remap subregister lanemasks before exchanging operands
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 4 20:36:14 PST 2016
Author: matze
Date: Fri Mar 4 22:36:13 2016
New Revision: 262768
URL: http://llvm.org/viewvc/llvm-project?rev=262768&view=rev
Log:
RegisterCoalescer: Remap subregister lanemasks before exchanging operands
Rematerializing and merging into a bigger register class at the same
time, requires the subregister range lanemasks getting remapped to the
new register class.
This fixes http://llvm.org/PR26805
Modified:
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=262768&r1=262767&r2=262768&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Fri Mar 4 22:36:13 2016
@@ -1007,8 +1007,14 @@ bool RegisterCoalescer::reMaterializeTri
NewRC = TRI->getCommonSubClass(NewRC, DefRC);
assert(NewRC && "subreg chosen for remat incompatible with instruction");
}
+ // Remap subranges to new lanemask and change register class.
+ LiveInterval &DstInt = LIS->getInterval(DstReg);
+ for (LiveInterval::SubRange &SR : DstInt.subranges()) {
+ SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
+ }
MRI->setRegClass(DstReg, NewRC);
+ // Update machine operands and add flags.
updateRegDefsUses(DstReg, DstReg, DstIdx);
NewMI->getOperand(0).setSubReg(NewIdx);
// Add dead subregister definitions if we are defining the whole register
@@ -1025,7 +1031,6 @@ bool RegisterCoalescer::reMaterializeTri
//
// at this point for the part that wasn't defined before we could have
// subranges missing the definition.
- LiveInterval &DstInt = LIS->getInterval(DstReg);
if (NewIdx == 0 && DstInt.hasSubRanges()) {
SlotIndex CurrIdx = LIS->getInstructionIndex(*NewMI);
SlotIndex DefIndex = CurrIdx.getRegSlot(NewMI->getOperand(0).isEarlyClobber());
Modified: llvm/trunk/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll?rev=262768&r1=262767&r2=262768&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll Fri Mar 4 22:36:13 2016
@@ -1,6 +1,5 @@
-; XFAIL: *
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s
-; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s
+; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null < %s
; The register coalescer introduces a verifier error which later
; results in a crash during scheduling.
More information about the llvm-commits
mailing list