[llvm] r262746 - [DAGCombine] Fix divrem combine not to assume div/rem type is simple.

[Michael Kuperstein via llvm-commits]

Author: mkuper
Date: Fri Mar  4 15:23:29 2016
New Revision: 262746

URL: http://llvm.org/viewvc/llvm-project?rev=262746&view=rev
Log:
[DAGCombine] Fix divrem combine not to assume div/rem type is simple.

The divrem combine assumed the type of the div/rem is simple, which isn't
necessarily true. This probably worked fine until r250825, since it only
saw legal types, but now breaks when it runs as a pre-type-legalization 
combine.

This fixes PR26835.

Differential Revision: http://reviews.llvm.org/D17878

Added:
    llvm/trunk/test/CodeGen/X86/pr26835.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=262746&r1=262745&r2=262746&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar  4 15:23:29 2016
@@ -2138,7 +2138,10 @@ SDValue DAGCombiner::visitMUL(SDNode *N)
 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
                                      const TargetLowering &TLI) {
   RTLIB::Libcall LC;
-  switch (Node->getSimpleValueType(0).SimpleTy) {
+  EVT NodeType = Node->getValueType(0);
+  if (!NodeType.isSimple())
+    return false;
+  switch (NodeType.getSimpleVT().SimpleTy) {
   default: return false; // No libcall for vector types.
   case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
   case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;

Added: llvm/trunk/test/CodeGen/X86/pr26835.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr26835.ll?rev=262746&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr26835.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr26835.ll Fri Mar  4 15:23:29 2016
@@ -0,0 +1,10 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux"
+
+; CHECK-LABEL: foo
+; CHECK: div
+define i24 @foo(i24 %a, i24 %b) {
+  %r = urem i24 %a, %b
+  ret i24 %r
+}